• 센서학회지
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• 제18권2호
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• pp.128-134
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• 2009

Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mV amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ${\pm}2.5\;V$ power supply are shown and compared with the simulated results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.383-390
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• 2014

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is $1.1mm^2$ including I/O pads.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1997년도 추계학술대회 학술발표 논문집
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• pp.3-5
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• 1997

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• 센서학회지
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• 제28권5호
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.7-11
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• 1998

In this paper, a new synapse cell with nonvolatile SONOS semiconductor memory device is proposed and it's fundamental function electronically implemented SONOS NVSM has shown characteristics that the memory value, synaptic weights, can be increased or decreased incrementally. A novel SONOS synapse is used to read out the stored analog value. For the purpose of synapse implementation using SONOS NVSM, this work has investigated multiplying characteristics including weight updating characteristics and neuron output characteristics. It is concluded that SONOS synapse cell has good agreement for use as a synapse in artificial neural networks.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.516-516
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• 2000

We propose a neuron model that is possible to learn three-dimensional movement. The neuron model by imitating structure of a neuron, has the system resemble a neuron. We considered a neuron system based on the arguments, and wished to examine whether the system had reasonable function. Koch, Poggio and Torre believed that inhibition signal would shunt excitation signal on the dendrites. They believed that excitation signal operated input-signals and inhibition did as delayed ones. Thus, they were sure that function for directional selectivity was arisen by the shunting. Koch's concept is so important; therefore, we construct the neuron system with their concept. The neuron system makes the shunting function; thus, the model may have a function for directional selectivity. We initialized the connections and the dendrites by random data, and trained them by the back-propagation algorithm for three-dimensional movement. We made sure the defection of three-dimensional movement in the system.

• 한국지능시스템학회논문지
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• 제24권5호
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• pp.457-461
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• 2014

생물학적 신경 세포의 모델링을 위한 펄스타입 실리콘 뉴런 회로를 $0.18{\mu}m$ CMOS 공정을 이용하여 반도체 집적회로로 설계하였다. 제안하는 뉴런 회로는 입력 전류신호를 위한 커패시터 입력단과, 출력 전압신호 생성을 위한 증폭단 및 펄스신호 초기화를 위한 MOS 스위치로 구성된다. 전압신호 입력을 전류신호 출력으로 변환하는 기능의 시냅스 회로는 몇 개의 PMOS와 NMOS 트랜지스터로 이루어지는 범프회로를 사용한다. 제안하는 뉴런 모델의 검증을 위하여, 2개의 뉴런과 시냅스가 직렬연결된 뉴런체인을 구성하여 SPICE 모의실험을 실시하였다. 모의실험 결과, 뉴런신호의 생성과 시냅스 전달특성의 정상적인 동작을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.462-462
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• 2000

In this paper, genetic algorithm (GA) is the technique to search for the optimal structures (i,e., the kind of neural network, the number of hidden neuron, ..) of the neural networks which are used approximating a given nonlinear function, In this paper, we used multi layer feed-forward neural network. The decision method of synapse weights of each neuron in each generation used back-propagation method. In this study, we simulated nonlinear function approximation in the temperature control system.

• Applied Microscopy
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• 제36권2호
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• pp.83-91
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• 2006

신경연접은 다양한 생리적 또는 병적 상태에 반응하여 구조 및 수적 변화를 보이며, 신경연접의 밀도 변화는 신경세포의 활성 조절에 중요한 역할을 하는 것으로 알려져 있다. 따라서 특정 생리적 또는 병적 상태에서 신경연접의 밀도 변화를 명확히 이해하기 위해서는 정확한 정량방법을 이용한 밀도 측정이 필수적이다. 본 연구에서는 physical disector법을 이용하여 흰쥐 뇌의 치아이랑에 위치하는 과립신경세포의 신경연접 수를 측정하였으며, 이를 통해 physical disector의 방법적 정확성을 확인하고자 하였다. 성체 흰쥐를 관류고정한 후 치아이랑의 연속 절편을 얻어 통상적인 전자현미경 시료제작법을 통해 Epon 혼합용액에 포매하였다. Physical disector법을 이용한 밀도 분석 시 연속절편의 정렬, 비교 및 disector frame이 필요하므로 Reconstruct 프로그램을 사용하였다. 동물 당 40장의 $1{\mu}m$ 연속절편을 제작하여 과립신경세포체의 밀도를 측정하였으며, 15장의 80nm연속절편으로부터 bidirectional disector법을 이용하여 과립신경세포와 내측 관통로(medial perforant path) 간 신경 연접의 밀도를 분석하였다. 과립신경세포의 세포체와 신경연접은 각각 과립층과 분자층에 위치하기 때문에 하나의 신경세포가 가지는 신경연접의 수를 측정하기 위해서는 각 층의 부피를 고려하는 것이 요구된다. 따라서 과립층에 대한 분자층의 부피비율을 측정하였다. 실험결과, 흰쥐 치아이랑에 위치하는 하나의 과립세포당 약 6,500개의 신경연접의 존재한다는 사실을 확인하였으며, 이는 다른 연구자들의 결과와 유사하였다. 본 연구로부터 physical disector법은 특정 생리적 또는 병적 조건에서 나타나는 신경세포 및 신경연접의 수적 변화를 정확히 측정할 수 있는 유용한 정량방법임을 알 수 있었다. 향후 physical disector법을 이용하여 다양한 실험동물모델의 신경연접 변화를 분석하는 것은 신경연접의 형태적 가소성을 이해하는데 이바지할 것으로 생각된다.