• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2061-2068
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• 2016

A Bloom filter is a space-efficient data structure popularly applied in many network algorithms. This paper proposes a vectored Bloom filter to provide a high-speed Internet protocol (IP) address lookup. While each hash index for a Bloom filter indicates one bit, which is used to identify the membership of the input, each index of the proposed vectored Bloom filter indicates a vector which is used to represent the membership and the output port for the input. Hence the proposed Bloom filter can complete the IP address lookup without accessing an off-chip hash table for most cases. Simulation results show that with a reasonable sized Bloom filter that can be stored using an on-chip memory, an IP address lookup can be performed with less than 0.0003 off-chip accesses on average in our proposed architecture.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.670-673
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• 2002

This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of design and simulation results we predict that about 300$\times$300 pixels can be integrated on a chip at 100nm CMOS technology, realizing very high-speed segmentation at about 1600sec per color image. Consequently real-time color-video segmentation will become possible in near future.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.367-370
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• 2002

In this paper, we propose a new node architecture LonWorh control Network for home network system environmint using power line communications. Using conventional Lon Work technology is a many disputable points for home network. LonWork network system needs high-cost development equipment. Moreover, conventional Lon Work system can not implement high-grade algorithms and variety application operation. because of the limitation of processing ability in Neuron chip. For that reason, the proposed structure is applicable to low-cost and more complex applications which are impossible in home network using conventional Lonworks structure. The proposed structure is implemented with some hardware and かone software for power line home network. The physical layer and the MAC layer of the LonTalk protocol within ton Work are implemented in hardware, which decreases the development costs communication processor. The upper of link layer of the LonTalk protocol is implemented with software, which decreases the development costs of software and increases the flexibility of tile system and increases the extension of the system. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network in home network. As a result, it is concluded that the proposed architecture provides increasing flexibility and decreasing cost of the system.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.509-512
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• 2008

Ubiquitous Computing System란, 언제 어디서나 통신 및 컴퓨팅이 가능하고 컴퓨팅 시스템이 상호간에 정보를 공유하고 협력하는 컴퓨팅 시스템이다. 이로써 기존의 컴퓨팅 환경과 같이 사용자와 컴퓨터간의 대화형 상호작용이 아닌 물리적인 환경 상황(Context)등을 시스템이 스스로 인식하고 이를 기반으로 사용자와의 상호 작용을 지원하는 상황인식 기술이 필수적인 요소로 부각되고 있다. 또한, Ubiquitous Computing System을 위해 사용자 및 주변 환경 정보를 감지하는 센서(Sensor) 기술이 필요하다. 하지만 사용자 및 주변 환경으로부터 입력되는 불확실하거나 모호한 상황정보에 대한 표현과 추론에 대한 연구는 부족한 실정이다. 본 논문은 이런 이유에서 Rule-based System을 기반으로 CRS와 DOS의 개념을 도입한 새로운 상황인식 기반의 Architecture를 제안하고, 이를 VHDL을 통해 SoC로 구현하였다. CRS를 통해 실시간으로 다양한 센서에서 들어오는 많은 데이터에 가중치를 부여하여 각 센서마다 중요도를 달리 부여한다. 이로써, System은 Sensor 입력 값의 중요도에 따라 처리 순서를 우선적으로 부여하여 처리 속도를 높인다. 또, DOS를 통해 각양각색의 사용자에게 획일적인 서비스를 제공하는 것이 아니라 상황 변화의 패턴에 따라 개별화되고 특화된 서비스를 제공한다. 마지막으로, Ubiquitous Computing System의 향후 발전 가능성을 예상하고, 본 논문에서 제시한 Context-aware Architecture에 의해 구현된 UoC의 유용성을 짐작해 본다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.