Browse > Article

Bit-level Array Structure Representation of Weight and Optimization Method to Design Pre-Trained Neural Network  

Lim, Guk-Chan (WLL Mobile Lab. LG Electronics Inc.)
Kwak, Woo-Young (WLL Mobile Lab. LG Electronics Inc.)
Lee, Hyun-Soo (Dept. of Computer Engineering Kyunghee Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.9, 2002 , pp. 37-44 More about this Journal
Abstract
This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.
Keywords
신경망;구현;어레이 구조;최적화;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Douglas J. Smith, 'HDL Chip Design', Doone Publications, pp. 286-296, 1996
2 Szabo T., Antoni L., Horvath G., Feher B., 'A full-parallel digital implementation for pre-trained NNs', IJCNN 2000, Proc., Vol 2, pp. 49-54, 2000   DOI
3 Szabo T., Feher B., Horvath G., 'Neural network implementation using distributed arithmetic', Proc. KES '98, Vol. 3, pp. 510-518, 1998   DOI
4 Manferd Glesner, Werner Pochmuller, 'Neurocomputers, an overview of neural networks in VLSI', Neural Computing, Chapman & Hall, 1994
5 James-Roxby P., Blodget B.A., 'Adapting constant multipliers in a neural network implementation', Field-Programmable Custom Computing Machines, IEEE Symposium, pp. 335-336, 2000   DOI
6 Amin H., Curtis K.M., Hayes-Gill B.R., 'Efficient two-dimensional systolic array architecture for multilayer neural network', Electronics Letters, Vol 33, Issue 24, pp 2055-2056, 1997
7 Bernie New, 'A distributed arithmetic approach to designing scalable DSP chips', EDN Design Feature, Vol. Aug-17, pp. 107-114, 1995
8 G.K. Ma and F.J. Taylor, 'Multiplier policies for digital signal processing', IEEE ASSP Mag., No. 1, pp. 6-10, 1990   DOI   ScienceOn
9 Benyamin D. and Luk W. and Villasenor J., 'Optimizing FPGA-based vector product designs', FCCM '99 Proc., pp. 188-197, 1999   DOI
10 Ma G.-K., Taylor F.J., 'Multiplier policies for digital signal processing', ASSP Magazine, Vol 7, Issue 1, pp. 6-20, 1990   DOI   ScienceOn