• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.160-169
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• 2002

An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• The Journal of the Acoustical Society of Korea
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• v.20 no.3
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• pp.83-90
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• 2001

Conventional SAW duplexer filters employ a 1/4 wavelength transmission line, which causes difficulty in fabrication of the strip line on the package. Its manufacturing process is also complicated, because it needs integrating process of the separate transmitting filter, receiving filter and isolation circuits. This paper concerns development of a new structure of the duplexer filter that has all the transmitting filter, the receiving filter and the isolation circuit as a one chip device. For composition of the duplexer, we design the component SAW ladder filters and the isolation network consisting of lumped inductor and capacitor elements. Performance of the whole duplexer is optimized by the nonlinear multivariable minimization of a proper target function, and the result is compared with that of commercial filters.

• Progress in Superconductivity
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• v.4 no.1
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.2
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• pp.176-184
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• 2011

As modern megalopolises become more complex and huge, convenience and safety of citizens are main components for a welfare state. In order to make safe society, telemetrics technology, which remotely measures the information of target system using electronic devices, is an essential component. In general, telemetrics technology consists of USN (ubiquitous sensor network) based on a wireless network, smart sensor, and SoC (system on chip). In the smart sensor technology, the following two problems should be overcome. Firstly, because it is very difficult for transducer manufacturers to develop smart sensors that support all the existing network protocols, the smart sensor must be independent of the type of networking protocols. Secondly, smart sensors should be modular so that a faulty sensor element can be replaced without replacing healthy communication element. To solve these problems, this paper investigates the feasibility of an IEEE 1451 based ZigBee smart sensor system. More specifically, a smart sensor for large network coverage has been developed using ZigBee for active telemetrics.

• Journal of information and communication convergence engineering
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• v.8 no.2
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• pp.219-222
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• 2010

An ubiquitous sensor network (USN) system to monitor the bio information and the emergency of the elderly in the silver town is presented. The USN system consists of the sensor node platforms based on MCU of Atmage128L and RF Chip of CC2420 satisfying IEEE 802.15.4, which includes the bios sensor module such as the electrocardiogram (ECG) sensor and the temperature sensor. Additionally, when an emergency of the elderly is occurred in the silver town, the routing algorithm suitable to find and inform the location of the elderly is proposed, and the proposed routing algorithm is applied to the USN. To collect and manage the ECG data at the PC connected to the sink node, LabView software is used. The bio information and the emergency of the elderly can also be monitored at the client PC by TCP/IP networks in the USN system.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.6
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• pp.339-343
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• 2012

Security and monitoring system has many applications and commonly used for detection, warning, alarm, etc. As the networking technology advances, user requirements are getting higher. An intelligent and cooperative surveillance system is proposed to meet current user demands and improve the performance. This paper focuses on the implementation issue for the embedded intelligent surveillance system. To cover wide area cooperative function is implemented and connected by wireless sensor network technology. Also to improve the performance lots of sensors are employed into the surveillance system to reduce the error but improve the detection probability. The proposed surveillance system is composed of vision sensor (camera), mic array sensor, PIR sensor, etc. Between the sensors, data is transferred by IEEE 802.11s or Zigbee protocol. We deployed a private network for the sensors and multiple gateways for better data throughput. The developed system is targeted to the traffic accident detection and alarm. However, its application can be easily changed to others by just changing software algorithm in a DSP chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1529-1539
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• 2000

The contact procedure of access channel necessary to set up the originating call has a close relation with the performance and capacity of the base station system in CDMA cellular network. This paper investigates the structure and the operation of the backward channel of IS-95 CDMA standard and explains the related system parameters. We can derive the throughput of the CDMA access channel depending on the arrivals of the access probes per access channel slot, given the system parameters such as cell radius, the maximum number of retransmission, and the error rates of the access and paging channel. It shows that the performance in throughput is much better in the CDMA IS-95 access channel than in the slotted aloha channel. It also gives the reasonable number of the trafic channels in a cell with the given blocking probability.