• Korean Journal of Materials Research
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• v.25 no.9
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• pp.429-434
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• 2015

Resistance switching memory cells were fabricated using atomically dispersed Pt-$SiO_2$ thin film prepared via RF co-sputtering. The memory cell can switch between a low-resistance-state and a high-resistance-state reversibly and reproducibly through applying alternate voltage polarities. Percolated conducting paths are the origin of the low-resistance-state, while trapping electrons in the negative U-center in the Pt-$SiO_2$ interface cause the high-resistance-state. Intermediate resistance-states are obtained through controlling the compliance current, which can be applied to multi-level operation for high memory density. It is found that the resistance value is related to the capacitance of the memory cell: a 265-fold increase in resistance induces a 2.68-fold increase in capacitance. The exponential growth model of the conducting paths can explain the quantitative relationship of resistance-capacitance. The model states that the conducting path generated in the early stage requires a larger area than that generated in the last stage, which results in a larger decrease in the capacitance.

• Polymer(Korea)
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• v.36 no.4
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• pp.519-524
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• 2012

Capacitance measurements of the polymer light-emitting diodes (PLEDs) with conjugated polyelectrolyte (CPE) electron transporting layers (ETLs) provide important information of device physics for understanding the function of CPEs as ETLs, together with current density-voltage-luminescence measurements. We investigated the counterion-dependent capacitance behaviors that present a highly negative or positive capacitance at the low frequency, and suggested different carrier injection mechanisms. Capacitance model study reveals that the electron injection mechanism can be described either by the dipole alignment scheme or by electronic charge carrier accumulation at the cathode/ETL/emission layer interfaces.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.262-268
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• 2010

In this paper, a high power active tunable bandpass filter made of dielectric resonators and varactor diodes is designed using the active capacitance circuit generating negative resistance for tuning cellular TX, RX band. An active capacitance circuit's series feedback circuit using GaAs HFET whose $P_{1dB}$ is 32 dBm is used for compensating the losses from the varactor diodes of the tunable bandpass filter. The tuning elements, the varactor diodes are used as the back-to-back configuration to achieve the high power performance, The designed active capacitance circuit improves the insertion loss characteristics. The designed 2-stage active tunable dielectric bandpass filter at cellular band can cover from 800 MHz to 900 MHz. The insertion losses at 836 MHz and 881.5 MHz with 25 MHz bandwidth are 0.48 dB and 0.39 dB, respectively. The $P_{1dB}$ of the designed bandpass filter at TX and RX band are measured as 19.5 dBm and 23 dBm, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.848-850
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• 2002

Single phase induction motor is directly used usual source, it can be a source of an appliance such as mechanical fan, refrigerator, washing machine, etc. Especially capacitor-run single phase induction motor is suitable to make more inexpensive and high efficient products because it is more high efficiency, and good to start than other single phase induction motors. Generally, voltage and current of capacitor-run single phase induction motor transfer to the part of positive phase and negative phase based on two motor theory. In this paper, we simulate the torque characteristics to capacitance variation from single phase induction motor's equivalent circuit. Through the test using the real motor, we compare and investigate the maximum torque of run state related with capacitance and the adequacy of the converted model.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.54 no.4
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• pp.163-170
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• 2005

This paper deals with an improved fault location algorithm with compensation ground capacitance through distributed parameter for a long parallel T/L. For the purpose of fault locating algorithm non-influenced by source impedance and fault resistance, the loop method was used in the system modeling analysis. This algorithm uses a positive and negative sequence of the fault current for high accuracy of fault locating calculation. Power system model of 160km and 300km long parallel T/L was simulated using EMTP software. To evaluate of the proposed algorithm, we used the several different cases 64 sampled data per cycle. The test results show that the proposed algorithm was minimized the error factor and speed of fault location estimation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.590-598
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• 2004

An active capacitance circuit which employs series feedback network for the implement of negative resistance and low noise operation is analyzed in depth and its application to low noise active RF BPF's is discussed. Whereas many authors reported a lot of circuits that embody negative resistance circuit most of them have concerns for the equivalent resistance and reactance value at the center frequency. In this case, it could be possible to face a problem that the negative resistance circuit becomes unstable, or have poor flatness in passband because of insufficient forecast for the negative resistance values as the frequency goes higher or lower. In this paper, we extracted the exact equivalent values of this circuit and analyzed the RF characteristics with the varying the values of active devices and feedback circuits and presented the method that the flatness of passband can be improved. We have designed a 4-pole active BPF, which has the bandwidth of 60 ㎒, 0.67 ㏈ insertion loss, 0.3 ㏈ ripple, and noise figure of 3.0 ㏈ at 1.99 ㎓ band.

• Journal of Mechanical Science and Technology
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• v.17 no.11
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• pp.1650-1658
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• 2003

This paper deals with a novel shunt circuit, which is capable of suppressing multimode vibration amplitudes by using a pair of piezoceramic patches. In order to describe the characteristic behaviors of a piezoelectric damper connected with a series and a parallel resistor-negative capacitor branch circuit, the stiffness ratio and loss factor with respect to the non-dimensional frequency are considered. The mechanism of the shunt damper is also described by considering a shunt voltage constrained by shunt impedance. To obtain a guideline model of the piezo/beam system with a negative capacitive shunting, the governing equations of motion are derived through the Hamilton's principle and a piezo sensor equation as well as a shunt-damping matrix is developed. The theoretical analysis shows that the piezo/beam system combined with a series and a parallel resistor-negative capacitor branch circuit developed in this study can significantly reduce the multiple-mode vibration amplitudes over the whole structural frequency range.