• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.267-267
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• 2013

Band engineering of a nanowire is related to the question what is the minimum size of a nanowire-based device. At the subnanometer scale, there has been a long standing problem whether it is possible to both control an energy band of an isolated nanowire by a dopant and measure it using angle-resolved photoemission spectroscopy (ARPES). This is because an extra atom in the subnanometer wire plays as a defect rather than a dopant and it is challenging to assemble isolated subnanometer wires into an array for an ARPES measurement. We demonstrate that only one of multiple metallic subnanometer wires canbe controlled electronically by a dopant maintaining the whole metallic bands of other wires, which was observed directly by ARPES. Here,the multiple metallic subnanometer wires were produced on a stepped Si(111) surface by a self-assembly method. The selective band engineering proves that the selectively-controlled metallic wire is nearly isolated electronically from other metallic wires and an electronic structure controlcan be realized down to subnanometer scale.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.451-456
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• 2014

A compact model of a depletion-mode silicon-nanowire (Si-NW) pH sensor is proposed. This drain current model is obtained from the Pao-Sah integral and the continuous charge-based model, which is derived by applying the parabolic potential approximation to the Poisson's equation in the cylindrical coordinate system. The threshold-voltage shift in the drain-current model is obtained by solving the nonlinear Poisson-Boltzmann equation for the electrolyte. The simulation results obtained from the proposed drain-current model for the Si-NW field-effect transistor (SiNWFET) agree well with those of the three-dimensional (3D) device simulation, and those from the Si-NW pH sensor model also agree with the experimental data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.12-15
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• 2008

The zinc oxide(ZnO) nanowires were deposited on Si(001) substrates by thermal chemical vapour deposition without any catalysts. SEM data suggested that the grown nanostructures were the well-aligned ZnO single crystals with preferential orientation. Back-gate ZnO nanowire field effect transistors(FET) were successfully fabricated using a photolithography process. The fabricated nanowire FET exhibits good contact between the ZnO nonowire and Au metal electrodes. Based on I-V characteristics it was found out that the ZnO nanowire revealed a characteristic of n-type field effect transistor. The drain current increases with increasing drain voltage, and the slopes of the $I_{ds}-V_{ds}$ curves are dependent on the gate voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.95-95
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• 2009

Single-crystalline Bi nanowires have motivated many researchers to investigate novel quasi-one-dimensional phenomena such as the wire-boundary scattering effect and quantum confinement effects due to their electron effective mass (~0.001 me). Single crystalline Bi nanowires were found to grow on as-sputtered films after thermal annealing at $270^{\circ}C$. This was facilitated by relaxation of stress between the film and the thermally oxidized Si substrate that originated from a mismatch of the thermal expansion. However, the method is known to produce relatively lower density of nanowires than that of other nanowire growth methods for device applications. In order to increase density of nanowire, we propose a method for enhancing compressive stress which is a driving force for nanowire growth. In this work, we report that the compressive stress can be controlled by modifying a substrate structure. A combination of photolithography and a reactive ion etching technique was used to fabricate patterns on a Si substrate. It was found that the nanowire density of a Bi film grown on $100{\mu}m{\times}100{\mu}m$ pattern Si substrate increased over seven times higher than that of a Bi sample grown on a normal substrate. Our results show that density of nanowire can be enhanced by sidewall effect in optimized proper pattern sizes for the Bi nanowire growth.

• Korean Journal of Materials Research
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• v.18 no.2
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• pp.103-106
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• 2008

The magneto-transport properties of an individual single crystalline Bi nanowire grown by a spontaneous growth method are reported. A four-terminal device based on an individual 400-nm-diameter nanowire was successfully fabricated using a plasma etching technique that removed an oxide layer that had formed on the surface of the nanowire. Large transverse ordinary magnetoresistance (1401%) and negative longitudinal ordinary magnetoresistance (-38%) were measured at 2 K. It was observed that the period of Shubnikov-de Haas oscillations in transverse geometry was $0.074^{T-1}$, $0.16^{T-1}$ and $0.77^{T-1}$, which is in good agreement with those of bulk Bi. However, it was found that the period of SdH oscillation in longitudinal geometry is $0.24^{T-1}$, which is larger than the value of $0.16^{T-1}$ reported for bulk Bi. The deviation is attributable to the spatial confinement arising from scattering at the nanowire surface boundary.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.115-119
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• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.793-798
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• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.26.2-26.2
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• 2009

A simple route of externalmechanical force is presented for enhancing the electrical properties ofpolymer nanocomposite consisted of nanowires. By dispersing ZnO nanowires inpolymer solution and drop casting on substrates, nanocomposite transistorscontaining ZnO nanowires are successfully fabricated. Even though the ZnOnanowires density is properly controlled for device fabrication, as-cast devicedoesn't show any detectablecurrents, because nanowires are separated far from each other with theinsulating polymer matrix intervening between them. Compared to the devicepressed at 300 kPa, the device pressed at 600 kPa currents increased by 50times showing the linear behavior against drain voltage and exhibits promisingelectrical properties, which operates in the depletion mode with highermobility and on-current. Such an improved device performance would be realizedby the contacts improvement and the increase of the number of electrical pathinduced by external force. This approach provides a viable solution for seriouscontact resistance problem of nanocomposite materials and promises for futuremanufacturing of high-performance devices.