• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.

• 한국정밀공학회지
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• 제30권1호
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• pp.128-133
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• 2013

Si Nanowire (Si-NW) arrays were fabricated by top-down method. A relatively simple method is suggested to fabricate suspended silicon nanowire arrays. This method allows for the production of suspended silicon nanowire arrays using anisotropic wet etching and conventional MEMS method of SOI (Silicon-On-Insulator) wafer. The dimensions of the fabricated nanowire arrays with the proposed method were evaluated and their effects on the Field Effect Transistor (FET) characteristics were discussed. Current-voltage (I-V) characteristics of the device with nanowire arrays were measured using a probe station and a semiconductor analyzer. The electrical properties of the device were characterized through leakage current, dielectric property, and threshold voltage. The results implied that the electrical characteristics of the fabricated device show the potential of being ion-selective field effect transistors (ISFETs) sensors.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.1-7
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• 2011

본 연구에서는 나노와이어 junctionless 트랜지스터의 문턱전압과 평탄전압을 위한 해석학적 모델링을 제시하였고 3차원 소자 시뮬레이션으로 검증하였다. 그리고 junctionless 트랜지스터의 소자설계 가이드라인을 설정하는 방법과 그 예를 제시하였다. 제시한 문턱전압과 평탄전압 모델은 3차원 시뮬레이션 결과와 잘 일치하였다. 나노와이어 반경과 게이트 산화층 두께가 클수록 또 채널 불순물 농도가 높을수록 문턱전압과 평탄전압은 감소하였다. 게이트 일함수와 원하는 구동전류/누설전류 비가 주어지면 나노와이어 반경, 게이트 산화층 두께, 채널 불순물 농도에 따른 junctionless 트랜지스터의 소자설계 가이드라인을 설정하였다. 나노와이어 반경이 작을수록 산화층의 두께가 얇을수록 채널 불순물 농도가 큰 소자를 설계할 수 있음을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• Applied Science and Convergence Technology
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• 제23권3호
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• pp.134-138
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• 2014

One-dimensional nanostructures such as nanowires have been extensively investigated as a promising type of material for applications of nanoscale technology. The fabrication of single-nanowire devices are consequently important and interesting. This study introduced a feasible method for growing CuO nanowires on Cu foils. The nanowires had diameters of 10~150 nm and lengths of more than $7{\mu}m$ and were grown by means of thermal oxidation in a vacuum. They were entirely and uniformly grown over the Cu foil surfaces and could be extracted and dispersed in an ethanol solution for further purposes. In addition, a simple fabrication method for realizing device functionality from a single CuO nanowire was reported. Fabricated devices were carefully checked by field-emission scanning electron microscopy (SEM). The probability of the realization of a single-CuO-nanowire device relative to that of all other types was estimated to be around 25%. Finally, the I-V characteristics of the devices were analyzed.

• EDISON SW 활용 경진대회 논문집
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• 제6회(2017년)
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• pp.412-416
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• 2017

CMOS device에서 off leakage current로 인한 power dissipation 문제는 미래 소자에 주어진 주요한 과제이다. Nanowire FET은 이러한 문제를 해결할 주요 미래소자로 각광받고있다. 하지만 nanowire FET을 공정할 때 채널 에칭을 완벽한 원형 구조로 가지는 것이 어렵기 때문에 타원형으로 시뮬레이션을 진행해 볼 필요성이 있다. 본 논문에서는 nanowire의 aspect ratio, crystal orientation의 변화에 따른 nanowire FET의 전압-전류 특성 및 transport 특성을 관찰하는 연구를 진행하였다. 시뮬레이션 결과, [100] 방향은 완벽한 원형구조에서 최적인 반면에 [110] 방향은 타원형으로 모델링함에 있어서 장점이 있는 것으로 나타났다.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2005년도 동계학술연구발표회 및 2차 아시안포럼
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• pp.116-116
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• 2005

• 전기학회논문지
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• 제66권10호
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• pp.1494-1498
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• 2017

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.