• Applied Science and Convergence Technology
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• v.24 no.2
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• pp.33-40
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• 2015

$ZrO_2$ and Al-Zr composite oxide film was prepared by vacuum assisted sol-gel dip coating method and anodizing. $ZrO_2$ films annealed above $400^{\circ}C$ have tetragonal structure. $ZrO_2$ layers inside etch pits were successfully coated from the $ZrO_2$ sol. The double layer structures of samples were obtained after being anodized at 100 V to 600 V. From the TEM images, it was found that the outer layer was $Al_2O_3$, the inner layer was multi-layer of $ZrO_2$, Al-Zr composite oxide and Al hydrate. The capacitance of $ZrO_2$ coated foil exhibited about 28.3% higher than that of non-coating foil after being anodized at 100 V. The high capacitance of $ZrO_2$ coated foils anodized at 100 V can be attributed to the relatively high percentage of inner layer in total thickness. The electrical properties, such as withstanding voltage and leakage current of coated and non-coated Al foils showed similar values. From the results, $ZrO_2$ and Al-Zr composite oxide is promising to be used as the partial dielectric of high voltage capacitor to increase the capacitance.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.85-85
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• 2012

For effective light harvesting, a design weighting should be implemented in a front geometry, in which the incident light transmits from a surface into a light-active layer. We designed a three-dimensionally patterned transparent conductor layer for effective light management. A transparent conductive oxide (TCO) film was formed as three-dimensional structures. This efficiently drives the incident light at the front surface into a Si absorber to yield a reduction in reflection and an enhancement of current. This indicates that an optimum architecture for a front TCO surface will provide an effective way for light management in solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.59-63
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• 2010

Immersion Sn plating was produced on Cu foil by distributing nano-sized diamonds (ND). The ND distributed on the coating surface broke the continuity of Sn-oxide layer, therefore leading to penetrate the molten solder through the oxide and retarding the wettability degradation during a reflow process. Furthermore, the ND in the Sn coating played a role of diffusion barrier for Sn atoms and decreased the growth rate of intermetallic compound ($Cu_6Sn_5$) layer during the solid-state aging. The study confirmed the importance of ND to improve the wettability and reliability of the Sn plating. Complete dispersion of the ND within the immersion Sn plating needs to be further developed for the electronic packaging applications.

• Korean Journal of Materials Research
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• v.25 no.11
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• pp.612-615
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• 2015

In this work, on-site corrosion behavior of heat resistant tubes of T91, used as components of a superheater in a power plant for up to 25,762 h, has been investigated using scanning electron microscopy(SEM), energy dispersive X-ray spectroscopy (EDS), and electron backscattered diffraction(EBSD), with the objectives of studying the composition, phase distribution, and evolution during service. A multi-layer structure of oxide scale was found on both the steamside and the fireside of the tube surface; the phase distribution was in the order of hematite/magnetite/spinel from the outer to the inner matrix on the steamside, and in the order of slag/magnetite/spinel from the outer to the inner matrix on the fireside. The magnetite layer was found to be rich in pores and cracks. The absence of a hematite layer on the fireside was considered to be due to the low oxygen partial pressure in the corrosion environment. The thicknesses of the hematite and of the slag-deposit layer were found to exhibit no significant change with the increase of the service time.

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• Journal of Hydrogen and New Energy
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• v.20 no.6
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• pp.485-491
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• 2009

In present work, NiO/YSZ anode functional layer was prepared by nano NiO powder and 8YSZ powder. The nano NiO powders were made by Pulsed wire evaporation (PWE) method. Nano NiO- YSZ functional layer was sintered at the temperature of $900-1400^{\circ}C$. The prepared functional layer was characterized by scanning electron microscopy (SEM) and electrochemical impedance spectroscopy. The nano NiO- YSZ anode functional layer sintered at $1300^{\circ}C$ shows the lowest polarization resistance. Nano NiO- YSZ anode functional layer shows about two times smaller polarization resistance than the anode functional layer made by commercial NiO-YSZ powders. Based on these experimental results, it is concluded that the nano NiO-YSZ cermet is suitable as a anode functional layer operated at $800^{\circ}C$.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.285-285
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• 2011

EUVL (Extreme Ultra Violet Lithography) is one of competitive lithographic technologies for sub-30nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance since the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.