• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.366-370
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• 2022

A 12 ㎛ pixel-sized 360 × 240 microbolometer focal plane array (MBFPA) was fabricated using a complementary metaloxide-semiconductor (CMOS)-compatible process. To release the MBFPA membrane, an amorphous carbon layer (ACL) processed at a low temperature (<400 ℃) was deposited as a sacrificial layer. The thermal time constant of the MBFPA was improved by using serpentine legs and controlling the thickness of the SiNx layers at 110, 130, and 150 nm on the membrane, with response times of 6.13, 6.28, and 7.48 msec, respectively. Boron-doped amorphous Si (a-Si), which exhibits a high-temperature coefficient of resistance (TCR) and CMOS compatibility, was deposited on top of the membrane as an IR absorption layer to provide heat energy transformation. The structural stability of the thin SiNx membrane and serpentine legs was observed using field-emission scanning electron microscopy (FE-SEM). The fabrication yield was evaluated by measuring the resistance of a representative pixel in the array, which was in the range of 0.8-1.2 Mohm (as designed). The yields for SiNx thicknesses of SiNx at 110, 130, and 150 nm were 75, 86, and 86%, respectively.

• Journal of Radiation Industry
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• v.8 no.3
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• pp.147-153
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• 2014

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a $2{\times}1$ butted CMOS image sensor module which except for the size of PCB is $170mm{\times}170mm$. And the pixel size is $55{\mu}m{\times}55{\mu}m$ and the number of pixels is $3,072{\times}3,072$. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2707-2712
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• 2011

In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.11
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• pp.1149-1155
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• 2004

In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.

• Journal of Sensor Science and Technology
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• v.18 no.2
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• pp.128-134
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• 2009

Integrated circuit of a new neuron chain with a synapse function for Hodgkin-Huxley model which is a good electrical model about a real biological neuron is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Pulse type neuron chain consist of series connected current controlled single neurons through synapses. For the realization of the single neuron, a pair of voltage mode oscillators using operational transconductance amplifiers and capacitors is used. The synapse block which is a connection element between neurons consist of a voltage-current conversion circuit using current mirror. SPICE simulation results of the proposed circuit show 160 mV amplitude pulse output and propagation of the signal through synapses. Measurements of the fabricated pulse type neuron chip in condition of ${\pm}2.5\;V$ power supply are shown and compared with the simulated results.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.16-22
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• 2009

Integrated circuit of a pulse-type neuron for Hodgkin-Huxley model is implemented in a $0.5{\mu}m$ 1 poly 2 metal CMOS technology. Proposed pulse-type neuron model consist of input stage with summing function and pulse generating block which make neuron pulse above threshold value. Pulse generating circuit consist of several transistors, capacitors and negative resistor with a charge supply function. SPICE simulation results show that neuron pulse is generated above threshold current of 70 nA. Measurements of the fabricated pulse type neuron chip in condition of 5 V power supply are shown and compared with the simulated results.

• Transactions on Electrical and Electronic Materials
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• v.12 no.5
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.14-18
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• 2010

In this paper, we describe a CMOS DC-DC converter with a variable output voltage(5-7V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L,C) has been designed and fabricated on a 0.5um 2-poly 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), cellular Phone, Laptop Computer, etc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.