• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.10 s.253
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• pp.1314-1319
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• 2006

This paper describes the novel fabrication method of the high-aspect-ratio nano structure which is impossible by conventional method using a shadow mask and a Deep X-ray Lithography (DXRL). The shadow mask with $1{\mu}m-sized$ apertures is fabricated on the silicon membrane using a conventional UV-lithography. The size of aperture is reduced to 200nm by accumulated low stress silicon nitride using a LPCVD (low pressure chemical vapor deposition) process. The X-ray mask is fabricated by depositing absorber layer (Au, $3{\mu}m$) on the back side of nano shadow mask. The thickness of an absorber layer must deposit dozens micrometers to obtain contrast more than 100 for a conventional DXRL process. The thickness of $3{\mu}m-absorber$ layer can get sufficient contrast using a central beam stop method, blocking high energy X-rays. The nano circle and nano line, 200nm in diameter in width, respectively, were demonstrated 700nm in height with a negative photoresist of SU-8.

• Journal of Magnetics
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• v.14 no.4
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• pp.168-171
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• 2009

We propose a new type of spin torque nano-oscillator structure with an exchange- biased free rotating layer. The proposed spin torque nano-oscillator consists of a fixed layer and a free rotating layer with an additional anti-ferromagnetic layer, which leads to an exchange bias in the free rotating layer. The spin dynamics of the exchange-biased free rotating layer can be described as an additional exchange field because the exchange bias manifests itself by the existance of a finite exchange bias field. The exchange bias field plays a similar role to that of a finite external field. Hence, microwave generation can be achieved without an external field in the proposed structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.139.1-139.1
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• 2007

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.118.2-118.2
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• 2008

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.634-634
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• 2013

Transfer molding methods have a problem that weak adhesion between nanostructures and substrates. It is important to make various nano scale applications, also the stability of nanostructure on substrate is related with device performance. We studied an effect of poly 4-vinylphenol (PVP) as the polymeric adhesion layer between organic nanowires and a Si substrate when the nanowires are transferred by liquid-bridge-mediated nanotransfer molding method (LB-nTM). Their structural stability was examined by optical microscopy, scanning electron microscopy as multiple transfer molding and washing process. Field-effect transistors were fabricated with organic semiconductor nanowires on a polymeric adhesion layer and their electrical properties showed no significant difference as the one without the adhesion layer. As a result, adhesion layer can be used in the washing process and making multi-layer nano-scale patterns.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1266-1269
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• 2007

Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.43-43
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• 2010

we have investigated the field emission characteristics of the CNT/TEOS hybrid thin films fabricated by a spray method. It is found that the CNT/TEOS hybrid emitters show high current density, low turn on field, and long-term emission stability compared to the CNT emitters. These efficient field emission characteristics of the CNT/TEOS hybrid emitters are attributed to the TEOS sol, acting as a protection layer of nanotube emitter by surrounding the nanotube tip as well as a binder material to enhance the adhesion of nanotube emitters to the substrate. Therefore, the CNT/TEOS hybrid emitters could be utilized as an alternative for the efficient and reliable field emitters.

• Journal of the Korean institute of surface engineering
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• v.47 no.3
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• pp.121-127
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• 2014

In this study, in order to improve corrosion resistance and wear resistance of aluminum, surface treatment was made by anodizing with oxalic acid solution and sealing with nano-diamond powder. Average size of nano-diamond powder was 30nm. Anodizing with oxalic acid made many pores in the aluminum oxide layer. Pore size and oxide thickness were investigated by scanning electron microscope (SEM). Pore size increased as temperature increased and voltage increased. It was possible to make oxide layer with pore diameter more than 50 nm. Oxide thickness increased as temperature and voltage and treatment time increased. Oxide layer with above $10{\mu}m$ thickness was made. Aluminum oxide layer with many pores was sealed by water with nano-diamond powder. Surface morphology was investigated by SEM. After sealing treatment with nano-diamond powder, corrosion resistance, wear resistance and hardness increased.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.6
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• pp.153-159
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• 2004

In this study, a new process to pattern directly on a thin metal layer using improved nano replication printing (nRP) process is suggested to evaluate the possibilities of fabricating a stamp for nano-imprinting. In the nRP process, any figure can be replicated from a bitmap figure file in the range of several micrometers with nano-scaled details. In the process, liquid-state resins are polymerized by two-photon absorption which is induced by femto-second laser. A thin gold layer was sputtered on a glass plate and then, designed patterns or figures were developed on the gold layer by newly developed top-down building approach. Generally, stamps fur nano-imprinting have been fabricated by using the costly electron-beam lithography process combined with a reactive ion-etching process. Through this study, the effectiveness of the improved nRP process is evaluated to make a stamp with the resolution of around 200nm with reduced cost.