• Annual Conference of KIPS
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.27-34
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• 2007

In this paper device driver for camera capture in hand held mobile system is implemented based on microsoft windows CE operating system. We also study the storage device driver based on the FAT fie system by using NAND flash memory as a storage device. We use the MBA2440 PDA board for implementing the hardware for image capture by using CMOS camera module producted by PixelPlus company. This camera module has VGA $640{\times}480$ pixel resolution. We also make application program which can be cooperated with the device driver for testing its performance, for example image capture speed and quality of captured image. We check that the application can be cooperated well not only with the device driver for camera capture but also with the device driver for FAT file system designed especially for the NAND flash memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.125-131
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• 2001

When the program voltage is applied to a word line, a part of the boosted channel charge in inhibited bit lines is lost due to the coupling between the string select line (SSL) and the adjacent word line. This phenomenon causes the program disturbance in the cells connected to the inhibited bit lines. This program disturbance becomes more serious, as the word line pitch is decreased. To reduce the word line coupling, the rising edge of the word-line voltage waveform was changed from a pulse step into a ramp waveform with a controlled slope. The word-line ramping circuit was composed of a timer, a decoder, a 8 b D/A converter, a comparator, and a high voltage switch pump (HVSP). The ramping voltage was generated by using a stepping waveform. The rising time and the stepping number of the word-line voltage for programming were set to $\mutextrm{m}-$ and 8, respectively,. The ramping circuit was used in a 512Mb NAND flash memory fabricated with a $0.15-\mutextrm{m}$ CMOS technology, reducing the SSL coupling voltage from 1.4V into a value below 0.4V.

• Journal of Internet Computing and Services
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• v.7 no.6
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• pp.105-112
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• 2006

This paper be composed to file system by making a new i_node structure which can decrease Write frequency because this's can improved the file system efficiency if reduced Write operation frequency of flash memory in respect of file system, i-node is designed to realize Cleaning policy of data in order to perform Write operation. This paper suggest Cleaning Algorithm for Write operation through a new i_node structure. In addition, this paper have mode the oldest data cleaned and the most recent data maintained longest as a result of experiment that the recent applied program and data tend to be implemented again through the concept of regional and time space which appears automatically when applied program is implemented. Through experiment and realization of the Flash file system, this paper proved the efficiency of NAND-type flash file system which is required in on Embedded system.

• Journal of the Korea Society of Computer and Information
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• v.28 no.8
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• pp.1-10
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• 2023

Recently, NAND flash memories have replaced magnetic disks due to non-volatility, high capacity and high resistance, in various computer systems but it has disadvantages which are the limited lifespan and imbalanced operation latency. Therefore, many page replacement policies have been studied to overcome the disadvantages of NAND flash memories. Although it is clear that these policies reflect execution characteristics of various environments and applications, researches on the foundation-policy decision for disk buffer management are insufficient. Thus, in this paper, we propose a foundation-policy recommendation model, called FRM for effectively utilizing NAND flash memories. FRM proposes a suitable page replacement policy by classifying and analyzing characteristics of workloads through machine learning. As an implementation case, we introduce FRM with a disk buffer management policy and in experiment results, prediction accuracy and weighted average of FRM shows 92.85% and 88.97%, by training dataset and validation dataset for foundation disk buffer management policy, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.378-388
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• 2008

Flash memory has been attracting attention as the next mass storage media for mobile computing systems such as notebook computers and UMPC(Ultra Mobile PC)s due to its low power consumption, high shock and vibration resistance, and small size. A storage system with flash memory excels in random read, sequential read, and sequential write. However, it comes short in random write because of flash memory's physical inability to overwrite data, unless first erased. To overcome this shortcoming, we propose an SSD(Solid State Disk) architecture with two novel features. First, we utilize non-volatile FRAM(Ferroelectric RAM) in conjunction with NAND flash memory, and produce a synergy of FRAM's fast access speed and ability to overwrite, and NAND flash memory's low and affordable price. Second, the architecture categorizes host write requests into small random writes and large sequential writes, and processes them with two different buffer management, optimized for each type of write request. This scheme has been implemented into an SSD prototype and evaluated with a standard PC environment benchmark. The result reveals that our architecture outperforms conventional HDD and other commercial SSDs by more than three times in the throughput for random access workloads.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.149-157
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• 2017

In this paper, we propose BCMR (Block Classification with Monitor and Restriction) to ensure the isolation and to reduce the interference of blocks between a garbage collection and a wear leveling. The proposed BCMR monitors an endurance variation of blocks during the garbage collection and detects hot blocks by making a restriction condition based on this information. The proposal induces a block classification by its update frequency for the garbage collection and the wear leveling, so we will get a prolonged lifetime of NAND flash memory systems. In a performance evaluation, BCMR prolonged the lifetime of NAND flash memory systems by 3.95%, on average and reduced a standard deviation per block by 7.4%, on average.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.6
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• pp.540-549
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• 2013

An adaptive non-uniform quantization scheme is proposed for soft-decision error correction in NAND flash memory. Even though the conventional maximizing mutual information (MMI) quantizer shows the optimal post-FEC (forward error correction) bit error rate (BER) performance, this quantization scheme demands heavy computational overheads due to the exhaustive search to find the optimal parameter values. The proposed quantization scheme has a simple structure that is constructed by only six parameters, and the optimal values of them are found by maximizing the mutual information between the input and the output symbols. It is demonstrated that the proposed quantization scheme improves the BER performance of soft-decision decoding with only small computational overheads.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.10
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• pp.245-250
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• 2019

The use of NAND flash memory has increased rapidly due to the development of mobile fields. However, NAND flash memory has a limited lifespan, so studies are underway to predict its lifespan. Workload is one of the factors that significantly affect the life of NAND flash memory, and workload analysis studies in mobile environments are insufficient. In this paper, we analyze the distribution of workload in the mobile environment by collecting traces generated by using Android-based smartphones. The collected traces can be divided into three groups of hotness. Also they are distributed in the form of heavy tails. We fit this to the Pareto, Lognormal, and Weibull distributions, and Traces are closest to the Pareto distribution.