• Journal of KIISE
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• v.42 no.8
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• pp.972-978
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• 2015

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.226-239
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• 2013

A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

• International journal of advanced smart convergence
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• v.12 no.1
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• pp.76-81
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• 2023

Journaling file systems are widely used to keep file systems in a consistent state against crash situations. As traditional journaling file systems are designed for block I/O devices like hard disks, they are not efficient for emerging byte-addressable NVM (non-volatile memory) media. In this article, we present a new in-memory journaling file system for NVM that is different from traditional journaling file systems in two respects. First, our file system journals only modified portions of metadata instead of whole blocks based on the byte-addressable I/O feature of NVM. Second, our file system bypasses the heavy software I/O stack while journaling by making use of an in-memory file system interface. Measurement studies using the IOzone benchmark show that the proposed file system performs 64.7% better than Ext4 on average.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.301-305
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• 2009

Pt nanoparticles with a narrow size distribution (dia. ~4 nm) were synthesized via an alcohol reduction method and used for the fabrication of hybrid Pt-$SiO_2$ nanoparticles. Also, the self-assembled monolayer of Pt nanoparticles (NPs) was studied as a charge trapping layer for non-volatile memory (NVM) applications. A metal-oxide-semiconductor (MOS) type memory device with Pt NPs exhibits a relatively large memory window. These results indicate that the self-assembled Pt NPs can be utilized for NVM devices. In addition, it was tried to show the control of thin-film thickness of hybrid Pt-$SiO_2$ nanoparticles indicating the possibility of much applications for the MOS type memory devices.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.157-163
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• 2021

A single write operation in a file system can modify multiple data, but these changes in the file system are not atomically written to disk. Thus, for the consistency of the file system, conventional journaling guarantees crash consistency instead of sacrificing the system performance. It is known that using non-volatile memory as a journal space can alleviate performance degradation due to low latency and byte-level accessibility of non-volatile memory. However, none of the journaling techniques considering non-volatile memory provide scalability. In this paper, journal space on non-volatile memory is divided into multiple regions for scalable journaling, thus dispersing concentrated operations in one region. Second, the journal area-specific operator structure is used to accelerate data write operations to storage devices. We apply the proposed technique to JFS to evaluate it on multi-core servers equipped with high-performance storage devices. The evaluation results show that the proposed technique performs better than the existing technique of the NVM-based journaling file system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.