DOI QR코드

DOI QR Code

Forgetting based File Cache Management Scheme for Non-Volatile Memory

데이터 망각을 활용한 비휘발성 메모리 기반 파일 캐시 관리 기법

  • Received : 2015.03.27
  • Accepted : 2015.05.11
  • Published : 2015.08.15

Abstract

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

비휘발성 메모리는 바이트 단위 접근과 비휘발성을 지원한다. 이러한 특성들은 비휘발성 메모리를 캐시, 메모리, 디스크와 같은 메모리 계층 구조 가운데 하나의 영역으로 사용을 가능케 한다. 비휘발성 메모리의 흥미로운 특성은 데이터 보존 기간이 실제로는 제한적인 기간을 가지고 있다는 것이다. 게다가 데이터 보존 기간과 쓰기 지연간의 트레이드오프가 존재 한다. 본 논문에서는 이를 활용하여 비휘발성 메모리를 파일 캐시로 사용하는 새로운 관리 기법을 제안한다. 제안하는 기법은 기존의 캐시 관리 기법과는 반대로 짧은 데이터 보존 시간으로 데이터를 저장하고 쓰기 성능을 개선한다. 제안하는 기법은 LRU 대비 평균 접근 지연 시간을 최대 31%, 평균 24.4%로 감소시킴을 보인다.

Keywords

Acknowledgement

Supported by : 한국연구재단

References

  1. Fan, D. H. C. Du, and D. Voigt, "H-ARC: A non-volatile memory based cache policy for solid state drives," MSST, 2014.
  2. Z. Liu, B. Wang, P. Carpenter, J. S. Li, Dongand Vetter, and W. Yu, "PCM-based durable write cache for fast disk I/O," MASCOTS, 2012.
  3. E. Lee, H. Bahn, and S. H. Noh, "Unioning of the buffer cache and journaling layers with non-volatile memory," FAST, 2013.
  4. JEDEC Solid State Technology Association. Stress-Test-Driven Qualification of Integrated Circuits, JESD47G.01, Apr. 2010. http://www.jedec.org/.
  5. A. Jog, A. K. Mishra, C. Xu, Y. Xie, V. Narayanan, R. Iyer, and D. C. R., "Cache revive: Architecting volatile STT-RAM caches for enhanced performance in cmps," DAC, 2012.
  6. R.-S. Liu, D.-Y. Shen, C.-L. Yang, S.-C. Yu, and C.-Y. M. Wang, "NVM duet: unified working memory and persistent store architecture," ASPLOS, 2014.
  7. K. Sankaranarayanan and K. Skadron, "Profile-based adaptation for cache decay," Transactions on Architecture and Code Optimization (TACO), Vol. 1, No. 3, pp. 305-322, Sep. 2004. https://doi.org/10.1145/1022969.1022972
  8. V. Phalke and B. Gopinath, "An inter-reference gap model for temporal locality in program behavior," SIGMETRICS, 1995.
  9. M. Awasthi, M. Shevgoor, K. Sudan, R. Balasubramonian, B. Rajendran, and V. Srinivasan, "Handling PCM resistance drift with device, circuit, architecture, and system solutions," Non-Volatile Memories Workshop, ser. NVMW, 2011.
  10. L. Jiang, B. Zhao, Y. Zhang, J. Yang, and B. R. Childers, "Improving write operations in MLC phase change memory," High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1-10, 2012.
  11. C. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. R. Stan, "Relaxing non-volatility for fast and energy-efficient STT-RAM caches," Proc. of the 17th IEEE Symposium on High Performance Computer Architecture, ser. HPCA, 2011.
  12. JESD218A:, "Solid-state drive (SSD) requirements and endurance test method," 2011, http://www.jedec.org/standards-documents/docs/jesd218a.
  13. D. Narayanan, A. Donnelly, and A. Rowstron, "Write off-loading: Practical power management for enterprise storage," ACM Transactions on Storage, Vol. 3, No. 4, 2008.
  14. A. Verma, R. Koller, L. Useche, and R. Rangaswami, "SRCMap: energy proportional storage using dynamic consolidation," Proc. of the 10th USENIX Conference on File and Storage Technologies, ser. FAST, 2010.