• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.291-293
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• 2000

In 64M DRAM, sub-1/4m NMOSFETs with STI(Shallow Trench Isolation), anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN interlayer induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel Boron dopant redistribution due to the defect should be considered to improve hump characteristics besides consideration of STI comer shape and recess.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.18-20
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• 2002

In sub-l/4 ${\mu}{\textrm}{m}$ NMOSFET with STI (Shallow Trench Isolation), the anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel boron dopant redistribution due to the defect should be considered to improve hump characteristics besides considerations of STI comer and recess. 130

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.82-90
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• 1995

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.154-155
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• 2008

대전류용 전력소자를 제조하기 위해 고밀도 트렌치를 형성하여 이들을 병렬로 연결시켜 트렌치 게이트 NMOSFET를 제작하였다. 고밀도 트렌치 소자를 제작한 후 케이트 산화막 두께에 따른 전류-전압 특성을 분석하였다. 트렌치 측벽의 게이트 산화막 두께는 트렌치 측벽의 결정방황에 따라 산화막 두께가 다르게 성장된다. 특히 게이트 산화막 두께의 균일도가 나쁘거나 두꺼울수록 케이트 전류-전압 특성은 다르게 나타난다. 트렌치 형상에 따라 측벽의 산화막 두께가 불균일하거나 혹은 코너 부분의 산화막이 두께가 앓게 증착됨을 알 수 있었다. 이는 트렌치 측벽의 결정방향에 따라 산화막 성장 두께가 다르기 때문이다. 이러한 산화막 두께의 균일도를 향상시키기 위해 트렌치 코너 형상을 개선하여 트렌치 측벽의 게이트 산화막의 두께 균일도를 높였으며, 그 결과 소자의 전기적 특성이 개선되었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.20-23
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• 2012

In this paper, we investigated the device performance on fluorine implantation, hot carrier reliability and RTS (random telegraph signal) noise characteristics of NMOSFETs. The capacitance of the fluorine implanted NMOSFET decreased due to the increase of the gate oxide thickness. RTS noise characteristics of the fluorine implated NMOSFET was improved approximately by 46% due to the decrease of trap density at Si/$SiO_2$ interface. The improved gate oxide quality also results in the longer hot carrier life time.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.353-353
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• 2012

채널 도핑이 다른 비대칭 구조를 갖는 NMOSFET의 게이트 전압에 따른 Drain saturation current (IDSAT), maximum transconductance (GM) 및 threshold voltage (VT)와 같은 다양한 변수를 측정하였고 DAHC (Drain avalanche hot carriers) 스트레스에 따른 특성을 추출하였다. 전기적 특성은 반도체 파라미터 분석기를 사용하여 Probe system에서 진행되었다. 문턱전압은 Normal channel dopoing의 경우 0.67 V, High channel doping의 경우 0.74 V로 High channel doping된 소자가 상대적으로 높은 문턱전압을 보였다. Swing의 경우 Normal channel doping의 경우 87 mV/decade, high channel doping의 경우 92 mV/decade으로 High channel doping된 소자가 더 높은 Swing값을 보였다. 스트레스 인가 후 두 소자 모두 문턱전압이 증가하고 ON-current가 감소하였다. High channel doing된 소자의 경우 Normal channel doping된 소자보다 문턱전압의 증가율과 Current 감소율 측면 모두 스트레스에 더 민감하게 반응하였다. 문턱전압이 서로 다른 비대칭 NMOSFET의 핫 캐리어 특성을 비교, 분석결과 스트레스 인가에 따라 채널 도핑이 높아질수록 드레인과 게이트간의 더 높은 전계가 생겨 게이트 산화막과 Si/SiO2 계면의 손상이 더 발생하였다. 따라서 채널 도핑이 상대적으로 높은 트랜지스터가 핫 캐리어에 의한 계면 트랩 생성 비율이 더 높다는 것을 알 수 있다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3626-3631
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• 2009

This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.806-808
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• 1992

This paper describes a buried-island SOI MOSFET structure which can reduce the edge channel effect by improving the interface properties at the side wall of active island and by reducing the strength of electric field applied at the upper corner of the side wall from the gate. Also, the buried-island SOl structure can obtain the uniform thickness of SOl film. The buried-island structure can be achieved by Zone- Melting-Recrystallization of polysilicon and polishing. Both simulated and experimental results show that the buried-island SOl NMOSFET has less edge channel effect than the conventional SOl NMOSFET using LOCOS or mesa isolation technique.