• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1962-1969
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• 2009

During past 20 years we have witnessed brilliant advances in major components of computer system, including CPU, memory, network device and HDD. Among these components, in spite of its tremendous advance in capacity, the HDD is the most performance dragging device until now and there is little affirmative forecasting that this problem will be resolved in the near future. We present a new approach to solve this problem using the NAND Flash memory. Researches utilizing Flash memory as storage medium are abundant these days, but almost all of them are targeted to mobile or embedded devices. Our research aims to develop the NAND Flash memory based storage system enough even for enterprise level server systems. This paper present structural and operational mechanism to overcome the weaknesses of existing NAND Flash memory based storage system, and its evaluation.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.1-9
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• 2021

3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, due to the nature of the lamination process, there is a problem that the frequency of error occurrence may vary depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of write/erase(P/E) operations of the flash memory increases. Most flash-based storage devices such as SSDs use ECC for error correction. Since this method provides a fixed strength of data protection for all flash memory pages, it has limitations in 3D NAND flash memory, where the error rate varies depending on the physical location. Therefore, in this paper, pages and layers with different error rates are classified into clusters through the K-means machine learning algorithm, and differentiated data protection strength is applied to each cluster. We classify pages and layers based on the number of errors measured after endurance test, where the error rate varies significantly for each page and layer, and add parity data to stripes for areas vulnerable to errors to provides differentiate data protection strength. We show the possibility that this differentiated data protection policy can contribute to the improvement of reliability and lifespan of 3D NAND flash memory compared to the protection techniques using RAID-like or ECC alone.

• Journal of the Korea Society of Computer and Information
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• v.22 no.4
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.651-660
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• 2008

Flash memory is widely used in embedded systems because of its benefits such as non-volatile, shock resistant, and low power consumption. However, NAND flash memory suffers from out-place-update, limited erase cycles, and page based read/write operations. To solve these problems, YAFFS and RFFS, the flash memory file systems, are proposed. However YAFFS takes long time to mount the file system, because all the files are scattered all around flash memory. Thus YAFFS needs to fully scan the flash memory. To provide fast mounting, RFFS has been proposed. It stores all the block information, the addresses of block information and meta data to use them at mounting time. However additional operations for the meta data management are decreasing the performance of the system. This paper presents a new NAND flash file system called ERFFS (Efficient and Reliable Flash File System) which provides fast mounting and recovery with minimum mata data management. Based on the experimental results, ERFFS reduces the flash mount/recovery time and the file system overhead.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.14-20
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• 2009

Recently, NAND flash memory is used not only for portable devices, but also for personal computers and server computers. Buffer cache replacement policies for the hard disks such as LRU and LFU are not good for NAND flash memories because they do not consider about the characteristics of NAND flash memory. CFLRU and its variants, CFLRU/C, CFLRU/E and DL-CFLRU/E(CFLRUs) are the buffer cache replacement policies considered about the characteristics of NAND flash memories, but their performances are not better than those of LRD. In this paper, we propose a new buffer cache replacement policy for NAND flash memory. Which is based on LFU and is taking into account the characteristics of NAND flash memory. And we estimate the performance of hit ratio and flush operation numbers. The proposed policy shows better hit ratio and the number of flush operation than any other policies.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.27-34
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• 2013

NAND Flash Memory has been used in several devices by low cost and high capacity, and the demand for mass NAND Flash Memory has increased due to the multimedia extension of mobile devices. The JFFS2, NILFS2, and YAFFS2 file systems are used mainly in NAND Flash Memory. In this paper, the performance of Sequential read/write of the 3 file systems are analyzed for the 4 I/O schedulers : CFQ(Complete Fair Queuing) I/O scheduler, NOOP(No Operation) I/O scheduler, Anticipatory I/O scheduler, and Deadline I/O scheduler. In JFFS2 file system, Anticipatory I/O scheduler has the best performance by 8% decreasing speed in writing time and 1.5% decreasing speed in reading time compared to the other I/O scheduler. In YAFFS2 file system, it results are similar to performance in reading and writing for the 4 I/O schedulers. In NILFS2 file system, NOOP I/O scheduler has 2% faster in writing and Deadline I/O scheduler has 6% faster in reading than other I/O schedulers.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.161-171
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• 2010

As embedded systems adopt monolithic kernels, NAND flash memory is used for swap space of virtual memory systems. While flash memory has the advantages of low-power consumption, shock-resistance and non-volatility, it requires garbage collections due to its erase-before-write characteristic. The efficiency of garbage collection scheme largely affects the performance of flash memory. This paper proposes a novel garbage collection technique which exploits data redundancy between the main memory and flash memory in flash memory-based virtual memory systems. The proposed scheme takes the locality of data into consideration to minimize the garbage collection overhead. Experimental results demonstrate that the proposed garbage collection scheme improves performance by 37% on average compared to previous schemes.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.75-84
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• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)