• 터널과지하공간
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• 제30권5호
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• pp.473-483
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• 2020

본 연구에서는 3차원 유한차분법(FDM) 프로그램인 FLAC3D를 이용하여 주방식 채광장을 모사하고 채굴적 형성에 의한 현지응력 교란으로 광주에 집중되는 수직응력의 변화를 분석하였다. 오차율과 해석시간을 고려하여 적절한 조합의 요소망 크기를 선정하고 지류론 암반을 모사하여 요소망 조합과 개발 심도에 따른 해석 성능을 검증하였다. 본 해석에서는 개발 영역 내에 1개(1×1)~ 121개(11×11)의 패널 광주가 생성되도록 채굴적을 형성하여 가장 높은 수준의 응력집중이 발생하는 중앙부 광주의 상부 수평단면에 작용하는 수직응력을 측정하였다. 40 m~320 m까지 40 m 단위로 굴착심도를 변경하여 동일한 과정을 반복 수행하였다. 해석 결과, 개발 규모(N_P)가 클수록, 개발심도(H_OB)가 작을수록 중앙부 광주의 수직응력 값이 지류론 추정값에 가까워지는 것을 확인하였다. 또한, 개발 규모가 작고 대심도인 경우에는 지류론에 의한 추정 시 수직응력이 과대평가될 수 있으며, 동일한 개발규모인 경우 심도가 증가할수록 수직응력계수(VSF)가 일정한 값으로 수렴하는 경향이 있음을 확인하였다.

• 전기전자학회논문지
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• 제17권3호
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 한국전기전자재료학회논문지
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• 제27권9호
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• Bulletin of the Korean Chemical Society
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• 제23권3호
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• pp.477-480
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• 2002

A new microporous TiO2-pillared layered titanate has been successfully prepared by hybridizing the exfoliated titanate with the anatase TiO2 nano-sol. According to the X-ray diffraction analysis and N2 adsorption-desorption isotherms, the TiO2-pillared layered titanate showed a pillar height of ~2 nm with a high surface area of ~460 m2/g and a pore size of ~0.95 nm, indicating that a microporous pillar structure is formed. Its photocatalytic activity was evaluated by measuring the photodegradation rate of 4-chlorophenol during irradiation of catalyst suspensions in an aqueous solution. An enhancement in activity of ca. 170% was obtained for TiO2-pillared layered titanate compared to that of the pristine compound such as layered cesium titanate.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.365-368
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• 2004

Charge compensation effects in multi-resurf structure make possible to obtain high breakdown volatage and low on-resistance in vertical MOSFET. In this paper, electrical characteristics of the vertical MOSFET with multi epitaxial layer is presented. Proposed device has n and p-pillar for obtaining the charge compensation effects and The doping concentration each pillar is varied from $5{\times}10^{14}\;to\;1{\times}10^{16}/cm^3$. The thickness of the proposed device also varied from $400{\mu}m\;to\;500{\mu}m$. Due to the charge compensation effects, 4500V of breakdown voltage can be obtained.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.613-617
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• 2014

This paper was analyzed electrical characteristics of super junction power MOSFET considering to charge imbalance. We extracted optimal design and process parameter at -15% of charge imbalance. Considering extracted design and process parameters, we fabricated super junction MOSFET and analyzed electrical characteristics. We obtained 600~650 V breakdown voltage, $224{\sim}240m{\Omega}$ on resistance. This paper was showed superior on resistance of super junction MOSFET. We can use for automobile industry.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 1998년도 제2회 박판성형심포지엄 논문집 박판성형기술의 현재와 미래
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• pp.102-109
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• 1998

In this study, the side panels were developed using the laser-welded Tailored Blanks (TB) with both the same thickness and the different thickness. At first, the formability of the same thickness T.B was investigated to be compared with one of the non welded panel with respect to weldline movements and strain distribution on blank during the stamping. Based on these results, we selected candidates of T.B with different thickness for stamping experiments. That is, we determined the weld line positions and the die step. Then we made some stamping tryouts with selected types of blank designs to investigate the formability of T.B with different thickness. During the tryouts, the wrinkles were found in the a-pillar lower region which is under the deformation mode of the shrink flange. In the b-pillar region, the fractures were found also, these defects have been reduced and corrected by controlling the blank design and the die faces and process pamameters.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.86-86
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• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.