• 제목/요약/키워드: N-drift layer

검색결과 33건 처리시간 0.024초

고내압 SiC-IGBT 소자 소형화에 관한 연구 (A Study on High Voltage SiC-IGBT Device Miniaturization)

  • 김성수;구상모
    • 한국전기전자재료학회논문지
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    • 제26권11호
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    • pp.785-789
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    • 2013
  • Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (~2.3 MV/cm), and high bulk electron mobility (~900 $cm^2/Vs$). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage ($V_B$= 1,600 V), lower on-resistance ($R_{on}$= 0.43 $m{\Omega}{\cdot}cm^2$) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

수중 수소 감지를 위한 MISFET형 센서제작과 그 특성 ($H_2$ sensor for detecting hydrogen in DI water using Pd membrane)

  • 조용수;손승현;최시형
    • 센서학회지
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    • 제9권2호
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    • pp.113-119
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    • 2000
  • 정류수 내 수소 가스를 감지할 수 있는 Pd 박막을 가진 Pd/Pt 게이트 MISFET 수소센서를 제조하였다. 감지게이트 MISFET와 기준 게이트 MISFET의 차동형 센서로 제작하여 MOSFET 고유의 드리프트를 최소화하였다. 수소유입으로 인한 드리프트는 $Si_3N_4/SiO_2$의 이중 게이트 절연막으로 줄였고, 수소에 의한 Pd의 격자 팽창에 의해 생기는 블리스터는 Pt을 넣어서 제거하였다. Pd 박막을 수소 여과기로 사용한 Pd/Pt 게이트 MISFET 센서로 측정한 결과 $0{\sim}500\;ppm$ 사이에서 선형적인 출력 특성을 얻을 수 있었다. 30 일간 $50^{\circ}C$의 정류수 속에서 장기안정도를 측정하였다. 전체적으로 감지 FET의 게이트 전압은 35 mV 상승하였고, 기준 FET는 48 mV 상승하여 안정한 특성을 나타내었다.

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Seasonal and local time variations of sporadic E layer over South Korea

  • Jo, Eunbyeol;Kim, Yong Ha;Moon, Suin;Kwak, Young-Sil
    • Journal of Astronomy and Space Sciences
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    • 제36권2호
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    • pp.61-68
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    • 2019
  • We have investigated the variations of sporadic E (Es) layer using the measurements of digisondes at Icheon ($37.14^{\circ}N$, $127.54^{\circ}E$, IC) and Jeju ($33.4^{\circ}N$, $126.30^{\circ}E$, JJ) in 2011-2018. The Es occurrence rate and its critical frequency (foEs) have peak values in summer at both IC and JJ in consistent with their known seasonal variations at mid-latitudes. The virtual height of the Es layer (h'Es) during equinox months is greater than that in other months. It may be related to the similar variation of meteor peak heights. The h'Es shows the semidiurnal variations with two peaks at early in the morning and late in the afternoon during equinoxes and summer. However, the semi-diurnal variation is not obvious in winter. The semi-diurnal variation is generally thought to be caused by the semi-diurnal tidal variation in the neutral wind shear, whose measurements, however, are rare and not available in the region of interest. To investigate the formation mechanism of Es, we have derived the vertical ion drift velocity using the Horizontal Wind Model (HWM) 14, International Geomagnetic Reference Field, and Naval Research Laboratory Mass Spectrometer and Incoherent Scatter Radar-00 models. Our results show that h'Es preferentially occur at the altitudes where the direction of the vertical ion velocity changes. This result indicates the significant role of ion convergence in the creation of Es.

Simulation and Fabrication Studies of Semi-superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

  • Na, Kyoung Il;Kim, Sang Gi;Koo, Jin Gun;Kim, Jong Dae;Yang, Yil Suk;Lee, Jin Ho
    • ETRI Journal
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    • 제34권6호
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    • pp.962-965
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    • 2012
  • In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.

다중BOX분할기법을 이용한 MOS FET의 강반전층내에서의 수직전계해석 (The Vertical Field Analysis within the Strong Inversion of MOS FET using the Multi-box Segmentation Technique)

  • 노영준;김철성
    • 한국통신학회논문지
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    • 제25권8B호
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    • pp.1469-1476
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    • 2000
  • 증가형 MOS FET에서 강반저의 경우 드레인 전류는 모두 드리프트에 기인하여 흐르기 때문에 I-V모델링시 수직전계와 수평전계를 함께 고려하여야한다. 특히 게이트전압 인가시 발생되는 수직전계는 표면이동도에 영향을 크게 주고 이로 인해서 캐리어들의 정상적인 흐름이 저해되는데 본 논문에서 제안한 다중 box분할법에 의하여 반전층의 깊이를 구하여 이동도 모델에 영향을 크게 미치는 반전층 내에서의 수직전계를 수치해석하였다.

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스마트 LED Driver ICs 패키지용 700 V급 Power MOSFET의 설계 최적화에 관한 연구 (Study on the Design of Power MOSFET for Smart LED Driver ICs Package)

  • 강이구
    • 한국전기전자재료학회논문지
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    • 제29권2호
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    • pp.75-78
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    • 2016
  • This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained $60{\mu}m$ N-drift layer depth, 791.29 V breakdown voltage, $0.248{\Omega}{\cdot}cm^2$ on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package.

Mixed-mode 시뮬레이션을 이용한 SiC DMOSFET의 스위칭 특성 분석 (Mixed-mode simulation of switching characteristics of SiC DMOSFETs)

  • 강민석;최창용;방욱;김상철;김남균;구상모
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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    • pp.37-38
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    • 2009
  • SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

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Effects of Isolation Period Difference and Beam-Column Stiffness Ratio on the Dynamic Response of Reinforced Concrete Buildings

  • Chun, Young-Soo;Hur, Moo-Won
    • International Journal of Concrete Structures and Materials
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    • 제9권4호
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    • pp.439-451
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    • 2015
  • This study analyzed the isolation effect for a 15-story reinforced concrete (RC) building with regard to changes in the beam-column stiffness ratio and the difference in the vibration period between the superstructure and an isolation layer in order to provide basic data that are needed to devise a framework for the design of isolated RC buildings. First, this analytical study proposes to design RC building frames by securing an isolation period that is at least 2.5 times longer than the natural vibration period of a superstructure and configuring a target isolation period that is 3.0 s or longer. To verify the proposed plan, shaking table tests were conducted on a scaled-down model of 15-story RC building installed with laminated rubber bearings. The experimental results indicate that the tested isolated structure, which complied with the proposed conditions, exhibited an almost constant response distribution, verifying that the behavior of the structure improved in terms of usability. The RC building's response to inter-story drift (which causes structural damage) was reduced by about one-third that of a non-isolated structure, thereby confirming that the safety of such a superstructure can be achieved through the building's improved seismic performance.

Fabrication of Superjunction Trench Gate Power MOSFETs Using BSG-Doped Deep Trench of p-Pillar

  • Kim, Sang Gi;Park, Hoon Soo;Na, Kyoung Il;Yoo, Seong Wook;Won, Jongil;Koo, Jin Gun;Chai, Sang Hoon;Park, Hyung-Moo;Yang, Yil Suk;Lee, Jin Ho
    • ETRI Journal
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    • 제35권4호
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    • pp.632-637
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    • 2013
  • In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

GFRP보강적층목재핀의 휨강도 및 인장형 전단내력 성능평가 (Performance Evaluation for Bending Strength and Tensile Type Shear Strength of GFRP Reinforced Laminated Wooden Pin)

  • 송요진;정홍주;김대길;김상일;홍순일
    • Journal of the Korean Wood Science and Technology
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    • 제42권3호
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    • pp.258-265
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    • 2014
  • 목구조물 접합부에 기존 드리프트핀(Drift pin)을 대체하고자 단판이나 합판을 유리섬유강화플라스틱(GFRP: Glass fiber reinforced plastic)과 복합 적층시킨 GFRP보강적층목재핀을 제작하였다. 더불어 GFRP보강적층목재핀을 사용하여 집성재 접합부의 인장형 전단내력 시험을 실시하였다. GFRP 배열에 따른 보강적층목재핀의 휨강도 시험결과 GFRP를 각층에 1장씩 삽입한 시험편(Type-A)이 가장 양호한 성능을 발휘하였다. 또한 압체압력 $1.96N/mm^2$, 온도 $150^{\circ}C$에서 한 시간 열압하여 고밀화한 시험편이 고밀화하지 않은 시험편과 비교하여 휨강도 성능이 1.57배 향상됨을 확인하였으며, 하중방향에 따라 Edgewise가 Flatwise보다 3.51배 높은 성능을 발휘하였다. 시험을 통해 가장 양호한 성능을 보인 Type-A 보강적층목재핀을 이용하여 전단내력 시험을 실시하였다. 접합구의 종류와 접합판의 종류를 달리하여 시험한 결과 드리프트핀과 강판을 적용한 시험체(Type-DS)와 비교하여 GFRP보강적층목재핀과 GFRP보강목재적층판을 적용한 시험체(Type-WL)가 1.12배 높은 전단내력이 측정되었으며 최대하중 이후에도 매우 양호한 인성이 관찰되었다.