• Journal of computational fluids engineering
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• v.14 no.4
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• pp.101-108
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• 2009

We present a new finite-element scheme for direct numerical simulation of particle suspensions in simple shear flow of a viscoelastic fluid in 3D. The sliding tri-periodic representative cell concept has been combined with DEVSS/DG finite element scheme by introducing constraint equations along the domain boundary. Rigid body motion of the freely suspended particle is described by the rigid-shell description and implemented by Lagrangian multipliers on particle boundaries. We present the bulk rheology of suspensions through the numerical examples of single-, two- and many-particle problems, which represent a large number of such systems in simple shear flow. We report the steady bulk viscosity and the first normal stress coefficient, which show shear-thickening behavior for both properties.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.711-714
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• 2000

In this paper, we propose a high-speed multiplier-free realization using ROM’s to store the results of coefficient scalings in Combination With higher signal rate and pipelined operations. We show that hardware multipliers are not needed. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or through-put). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that With Proper Choices of the Parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1029-1032
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• 2000

A neuro-fuzzy based circuit to recognize circuit pat-terns is proposed in this paper. The simple algorithm and exemption from the use of template patterns as well as multipliers enable the proposed circuit to implement on the hardware of an economical scale. Furthermore, thanks to the circuit design by using current-mode techniques, the proposed circuit call achieve easy extendability of tile circuit and efficient pattern recognition with high-speed. The validity of the proposed algorithm and tile circuit design is confirmed by computer simulations. The proposed pattern recognition circuit is integrable by a standard CMOS technology.

• Journal of IKEEE
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• v.19 no.2
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• pp.271-275
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• 2015

This paper proposes a unified HEVC $4{\times}4$ IDCT/IDST architecture for area reduction. In general, $4{\times}4$ IDCT and $4{\times}4$ IDST blocks are implemented separately, and they are connected with multiplexers. In the proposed arechitecture, these two blocks are unified, and internal hardware resources such as multipliers are shared. This reduces the chip area. The synthesized block in 0.18 um technology is 2,795 gates, and the gate count is reduced by 9.44% in comparison with conventional designs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Kyungpook Mathematical Journal
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• v.28 no.1
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• pp.23-34
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• 1988

A version of Ascoli's Theorem (equating compact and equicontinuous sets) is presented in the context of convergence spaces. This theorem and another, (involving equicontinuity) are applied to characterize compact subsets of quasi-multipliers of a $C^*$-algebra B, and to characterize the compact subsets of the state space of B. The classical Ascoli Theorem states that, for pointwise pre-compact families F of continuous functions from a locally compact space Y to a complete Hausdorff uniform space Z, equicontinuity of F is equivalent to relative compactness in the compact-open topology([4] 7.17). Though this is one of the most important theorems of modern analysis, there are some applications of the ideas inherent in this theorem which arc not readily accessible by direct appeal to the theorem. When one passes to so-called "non-commutative analysis", analysis of non-commutative $C^*$-algebras, the analogue of Y may not be relatively compact, while the conclusion of Ascoli's Theorem still holds. Consequently it seems plausible to establish a more general Ascoli Theorem which will directly apply to these examples.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.1
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• pp.43-48
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• 2004

This paper presents new architectures based on the linear feedback shia resister architecture over GF(2m). First we design a modular multiplier and a modular squarer, then propose an architecture by combing the multiplier and the squarer. All architectures use an irreducible AOP (All One Polynomial) as a modulus, which has the properties of all coefficients with '1'. The proposed architectures have lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponentiation architecture, which is the con operation in public-key cryptosystems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.166-175
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• 1990

The conventional FIR filters can be very expensive to implement due to the complexity of multibit multipliers. This paper presents an new type of multiplierless structure which is particularly suited to the hardware implementation of small, low cost, low power, high speed digital filters. The filter structures consisting of a transversal filter with tap coefficiented to the combination of two elements of the set {0, $\pm$$2^n$;n = integer} and cascaded with a integrator are proposed. Performance has been tested via simulation on a digital computer, and the results show that the response characteristics of presented filters are as equally good as those of conventional finitewordlength filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.577-583
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• 2000

An efficient echo cancellation method, which controls the echo caused from the PSTN, is proposed. In our situation, the PSTN is connected to the mobile subscriber and the base-station which use different bit-rate CVSD(continuously variable slope delta modulation) coders and echo canceller is installed at the location of the base-station. By using the symmetry of the coder pairs. the proposed method shortens the echo pate length and reduces the nonlinear distortion inherent in the coders. And it is implemented in the decoded signal region, so fitted to the general-purpose DSP implementation. We also proposed a echo cancellation method using the combined bit-stream so as to implement without the multipliers onto the VLSI. It has an improved echo cancellation performance by reducing the high frequency noises in the coders. And it has an reduced complexity by reducing the excitation rate of the bit-stream.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1365-1371
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• 2013

We have introduced two dimensional cluster aggregation model to explain theoretically two phase coexistence phenomena such that adsorption is increased sharply discontinuous in particular pressure on the surface. And then, we have derived adsorption isotherms by applying fundamental statistical thermodynamics and Lagrange multipliers to the our model. By analyzing the our derived adsorption isotherms, we can explain well qualitatively that two phase coexistence on the surface adsorption would be a phenomena that occurs with the strong attractive forces between the adsorbed particles.