• Transactions of The Korea Fluid Power Systems Society
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• v.8 no.3
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• pp.14-20
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• 2011

This study aims at aligning multiple wafers to reduce wafer handling time in wafer processes. We designed a multilevel structure for a prealigner which can handle multiple wafer simultaneously in a system. The system consists of gripping parts, kinematic parts, vacuum chucks, pneumatic units, hall sensors and a DSP controller. Aligning procedure has two steps: mechanical gripping and notch finding. In the first step, a wafer is aligned in XY directions using 4-point mechanical contact. The rotational error can be found by detecting a signal in a notch using hall sensors. A dual prealigner was designed for 300mm wafers and constructed for a performance test. The accuracy was monitored by checking the movement of a notch in a machine vision. The result shows that the dual prealigner has enough performance as commercial products.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.91-96
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• 2018

In this study temperature distribution and gas flow inside a planetary type reactor in which a number of satellites on a spinning susceptor were rotating were analyzed using numerical simulation. Effects of flow rates on gas flow and temperature distribution were investigated in order to obtain design parameters. The commercial computational fluid dynamics software CFD-ACE+ was used in this study. The multiple-frame-of-reference was used to solve continuity, momentum and energy conservation equations which governed the transport phenomena inside the reactor. Kinetic theory was used to describe the physical properties of gas mixture. Effects of the rotation speed of the satellites was clearly seen when the inlet flow rate was small. Thickness of the boundary layer affected by the satellites rotation became very thin as the flow rate increased. The temperature field was little affected by the incoming flow rate of precursors.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.79-83
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• 2007

We have developed a compact and cost-effective camera module on the basis of wafer-scale replication technology. A multiple-layered structure of several aspheric lenses in a mobile camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. We have demonstrated a VGA camera module fabricated by the wafer-scale replication processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having 200 um sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in order to achieve a higher resolution in wafer-scaled lenses for mobile camera modules.

• Journal of Korean Institute of Industrial Engineers
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• v.34 no.3
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• pp.296-307
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• 2008

A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.

• Journal of the Optical Society of Korea
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• v.10 no.3
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• pp.124-129
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• 2006

We have developed a compact and cost-effective camera module on the basis of wafer-scale-replica processing. A multiple-layered structure of several aspheric lenses in a mobile-phone camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. This wafer-scale processing leads to at least 95% yield in mass-production, and potentially to a very slim phone with camera-module less than 2 mm in thickness. We have demonstrated a VGA camera module fabricated by the wafer-scale-replica processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having $230{\mu}m$ sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in orderto achieve a higher resolution in wafer-scaled lenses for mobile-phone camera modules.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.839-844
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• 2003

This paper presents a method to segment wafer ID marks on poor quality images under uncontrolled lighting conditions of the semiconductor process. The active multiple templates matching method is suggested to search ID areas on wafers and segment them into meaningful regions and it would have been impossible to recognize characters using general OCR algorithms. This active template model is designed by applying a snake model that is used for active contour tracking. Active multiple template model searches character areas and segments them into single characters optimally, tracking each character that can vary in a flexible manner according to string configurations. Applying active multiple templates, the optimization of the snake energy is done using Greedy algorithm, to maximize its efficiency by automatically controlling each template gap. These vary according to the configuration of character string. Experimental results using wafer images from real FA environment are presented.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.47-52
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• 2008

We present a 3-D profiler specially devised for the profile measurement of rough surfaces that are difficult to be measured with conventional non-contact interferometer. The profiler comprises multiple two-point-diffraction sources made of single-mode optical fibers. Test measurement proves that the proposed profiler is well suited for the warpage inspection of microelectronics components with rough surface, such as unpolished backsides of silicon wafers and plastic molds of integrated-circuit chip package.

• Current Photovoltaic Research
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• v.5 no.2
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• pp.55-58
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• 2017

We investigated the influences of dielectric thin film coating on the optical characteristics of c-Si wafers with nanocone (NC) arrays using finite-difference time-domain (FDTD) simulations. Dielectric thin films on high-refractive-index surface can lower optical reflection and reflection dips appear at the wavelengths where destructive interference occurs. The optical reflection of the NC arrays was lower than that of the dielectric-coated planar wafer in broad wavelength range. Remarkable antireflection effects of the NC array could be attributed to beneficial roles of the NCs, including the graded refractive index, multiple reflection, diffraction, and Mie resonance. Dielectric thin films modified the optical reflection spectra of the NC arrays, which could not be explained by the interference alone. The optical properties of the dielectric-coated NC arrays were determined by the inherent optical characteristics of the NC arrays.

• Design & Manufacturing
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• v.18 no.2
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• pp.9-16
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• 2024

Recently, there has been extensive research conducted on the miniaturization of semiconductors and the improvement of their integration to achieve high-quality and high-performance electronic devices. To integrate and miniaturize multiple semiconductors, thin and precise wafers are essential. The backgrinding process, which involves high-precision processing, is necessary to achieve this. The backgrinding system is used to grind and polish the back side of the wafer to reduce its thickness to ㎛ units. This enables the high integration and miniaturization of semiconductors and a flattening process to allow for detailed circuit design, ultimately leading to the production of IC chips. As the backgrinding system performs precision processing at the ㎛ unit, it is crucial to determine the stability of the equipment's rigidity. Additionally, the flatness and surface roughness of the processed wafer must be checked to confirm the processability of the backgrinding system. IIn this paper, the goal is to verify the processability of the back grinding system by analyzing the natural frequency and resonance frequency of the equipment through computer simulation and measuring and analyzing the flatness and surface roughness of wafers processed with backgrinding system. It was confirmed whether processing damage occurred due to vibration during the backgrinding process.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.