• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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• pp.144-148
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). To improve the unbalanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• Journal of Power Electronics
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• 제16권4호
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• 제10권4호
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• pp.365-373
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• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• Journal of Power Electronics
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• 제17권1호
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• 조명전기설비학회논문지
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• 제20권3호
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• pp.36-44
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• 2006

일반적으로 PWM인버터에 발생된 고조파와 노이즈는 스위칭 주파수, dv/dt와 di/dt, PWM 스위칭 방법에 의해 영향을 받는다. 멀티레벨 인버터가 고전력 시스템에 적용되어 낮은 주파수에서 동작할 때 이것은 큰 고조파 성분과 노이즈를 발생하게 된다. 따라서 멀티레벨 인버터에 출력 필터가 요구된다. 본 논문에서는 H-bridge 7레벨 인버터 시스템을 사용한 3상 유도 전동기 구동 시스템의 고조파와 노이즈 감소를 위해 출력 필터를 설계하였다. 가격이 저렴하고 간단한 구조를 가지며, 고조파와 노이즈를 효과적으로 감소시킬 수 있는 수동필터는 멀티레벨 인버터 시스템을 사용한 3상 유도전동기 구동시스템에 적용되었다. 설계된 시스템은 향상되었고, 시뮬레이션과 실험을 통해 그 타당성을 증명하였다.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제18권4호
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.

• Journal of information and communication convergence engineering
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• 제1권3호
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• pp.163-168
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• 2003

This paper presents a cascade multilevel PWM rectifier without the isolation transformers for energy build-up at each inverter modules. The features and advantages of the proposed PWM rectifier can be summarized as follows; I) It realizes the high power high voltage AC/DC power conversion, 2) It uses no transformer which is bulky and heavy, 3) It has hybrid structure so that switching devices can be effectively utilized, 4) It produces high quality AC current even in high power high voltage applications, 5) The input power factor remains unity by simple modulation index control. The multilevel rectifier is analyzed by using the circuit DQ transformation whereby the characteristics and control equations are obtained. Finally, it will be shown that the system simulation reveals the validity of analyses.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 춘계학술대회 논문집
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• pp.1473-1479
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• 2011

In this paper, speed control of IPMSM drives for the next generation domestic high speed railway system using multilevel inverter is presented. Multilevel inverter is suitable for the high-voltage high-capacity motor drive system because noise and switching frequency of power semiconductor devices is reduced. For the speed control of IPMSM using multilevel inverter, maximum torque control is applied in a constant torque region, and field weakening control is applied in a constant power region. Simulation programs based on Matlab/Simulink are developed. Finally the designed system is verified by simulation and their characteristics are analyzed by the simulation results.

• Journal of Power Electronics
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• 제16권3호
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• pp.861-871
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• 2016

With high penetration of renewable energies, power electronic transformers (PETs) will be one of the most important infrastructures in the future power delivery and management system. In this study, an isolated bidirectional modular multilevel DC/DC converter is proposed for PET applications. A modular multilevel structure is adopted as switching valves to sustain medium voltages to achieve modular design and high reliability. Only one high-frequency transformer is used in the proposed converter, which significantly simplifies the circuit and galvanic insulation design. A dual-phase-shift modulation strategy is proposed to regulate the output power and achieve a simple voltage balancing control. A down-scaled (2 kW/20 kHz) prototype is constructed to demonstrate the proposed converter and verify the control strategy. The experimental results comply with the theoretical analysis well, with the highest power efficiency reaching 97.6%.