• Composites Research
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• 제35권3호
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• pp.182-187
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• 2022

본 논문은 다층 PCB에 사용되는 프리프레그의 물성을 파악하여 제시한 두께 실험식을 통해 PCB의 두께를 예측하기 위한 연구를 수행하였다. 프리프레그는 물성과 동박 잔존율에 의해서 PCB 제작시 두께가 감소하기 때문에 두께 실험식을 통한 정확한 PCB의 두께 예측이 필요하다. 두께 실험식에 사용되는 프리프레그의 밀도를 파악하기 위해 질량 및 두께를 측정하여 밀도를 도출하였다. 이후 CCL을 제작하기 위해 프리프레그와 동박을 적층하여 핫 프레스기를 사용하였고 광학현미경과 마이크로미터를 사용하여 두께를 측정하였다. 또한 동박 잔존율에 따른 두께 변화를 측정하기 위해 회로밀도를 다르게 구성하여 8층 PCB를 설계하였고 두께 측정 결과와 두께 실험식으로 도출된 두께를 비교하여 두께 실험식을 검증하였다. 비교 결과 CCL의 경우 2.56%, 다층 PCB의 경우 4.48%의 오차를 보였고 이를 통해 두께실험식의 신뢰성을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.150-152
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• 2004

The number of layers in rigid PCB(printed circuit board) is restricted, so the number of components can be embedded in module is restricted also. But using flexible multilayer PCB, the layers over than 7 can be evaluated. In this study, to verify the possibility of application of flexible multilayer PCB to RF modules, multilayered embedded capacitor is fabricated and analyzed. The characteristics of embedded capacitor is analyzed and compared to that of MLCC and LTCC capacitor. Embedded capacitor has better electrical features than MLCC and compatible one to LTCC capacitor.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2004년도 춘계학술발표대회 및 제6회 신소재 심포지엄
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• pp.38-38
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• 2004

• 반도체디스플레이기술학회지
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• 제22권1호
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• pp.94-98
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• 2023

In the case of high-speed data transmission on high multilayer boards, signal coherence is a problem, especially due to the via hole, and a solution to improve return loss or insertion loss by applying a back drill to the via hole is being proposed. In this paper, Near-Field Electromagnetic measurements were made on a high multilayer board to determine how the presence or absence of back drill affects signal consistency. For this purpose, we used a signal generator, spectrum analyzer, and EMC scanner on a test board to determine if it is possible to distinguish between areas with and without back drill in the via holes of the stubs on the board. Also, we analyzed the measured value of S11, S21 and EMC etc. for how much it improves the signal attenuation of the stub with back drill. Through this, we knew that less electromagnetic waves are generated the stub via with back drill. At future research, we will analyze how much it improves the signal loss and electromagnetic waves due to the depth of back drill.

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• 전자공학회논문지S
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• 제34S권11호
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• pp.34-42
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• 1997

In this paper, we show an optimal structure of impedance control in high density layouts ina high multilayers PCB. The impedance control in a high multilayers FR-4 PCB is very portant isue because a dielectric layer's thickness is very thin. Especially, odd mode impedance control is more difficult than characteristic impedance control in high multilayers PCB. So, we show an optimal structure of odd mode impedance control in that dielectric thickness is about 0.1mm with limited state and discuss multilayers PCB's for swich circuti pack and backplane in developing algorith scale ATM witching system in next time.

• 전자공학회논문지A
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• 제33A권10호
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• pp.61-70
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• 1996

In this paper, we find the values of near-end crosstalk coefficient in striplines of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, and define calcualtion errors in an analytic method and define the application range, and simualte near-end crosstalk coefficients of the FCT (fast CMOS TTL) in complicated striplines by HSPICE and analyze near-en crosstalk coefficients in relation to dielectric thickness and trace spaces of striplines. As a result, we analyze coupling structure of the near-end crosstalk in the coplicated sstriplines that are impedance matched and define a coupling formula of near-end crosstalk coefficients in general complicated striplines. Especially, it is approximated in the layout grade rule.

• 전자공학회논문지S
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• 제35S권4호
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• pp.20-29
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• 1998

In this paper, we find the values of near-end crosstalk coefficients in dual-offset stripline of a FR-4 multilayer PCB by an analytic method and a HSPICE simulation method, define calculation errors inananlytic method and the application range, simulate near-end crosstalk coefficients of the FCT(Fast CMOS TTL) in complicated dual-offset stripline by HSPICE and analyze near-end crosstalk and far-end crosstalk coefficients in dual-offset stripline. So, we analyze coupling structure of the near-end crosstalk and far-end crosstalk in the complicated dual-offset striplines that are 1[pF] capacitors termainated, and define a coupling formula of near-end crosstalk and far-end crosstalk coefficients dual-offset striplines.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.73-81
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• 2011

초고속 디지털 통신시스템의 성능은 빠른 에지율(edge rate), 클럭속도 및 디지털 정보전송방법 등에 영향을 받는다. 특히 고주파 통신시스템의 잡음원은 다수 전송선에서의 신호 간 동시 스위칭, 전원 공급, 신호 반사와 왜곡 등에 의해 발생하며, 다층(multilayer) PCB를 설계할 경우 신호의 충실성이 더욱 훼손된다. 따라서 시스템 H/W의 신호충실성을 얻기 위해 최적 임피던스 정합을 갖는 PCB 설계가 필요하다. 본 논문에서는 시스템 신호의 충실성을 위하여 다층 PCB 선로의 패턴에 따른 트랙계산 이론, 설계에 필요한 임피던스 및 특성 자동 분석 시뮬레이터를 개발한다. 특히 다층으로 PCB를 설계할 때 신호선과 접지부분 배치를 사전에 컴퓨터 모의실험을 통하여 최적조건의 임피던스에 맞는 설계가 가능하도록 시뮬레이터를 개발함은 물론 이를 데이터베이스화한다. 그리하여 제안된 시뮬레이션 툴은 PCB 설계 시 소요되는 시간을 단축하고 경제적인 PCB 개발을 가능케 한다.

• 반도체디스플레이기술학회지
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• 제17권1호
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• pp.62-65
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• 2018

In the era of the 4th Industrial Revolution, IoT products of various and specialized fields are being developed and produced. Especially, the generation of the artificial intelligence, robotic technology Multilayer substrates and packaging technologies in the notebook, mobile device, display and semiconductor component industries are demanding the need for flexible materials along with miniaturization and thinning. To do this, this work use FCCL (Flexible Copper Clad Laminate), which is a flexible printed circuit board (PCB), to implement FPCB (Flexible PCB), COF (Chip on Film) Use is known to be essential. In this paper, I propose a transfer device which prevents the occurrence of scratches by analyzing the mechanism of wrinkle and scratch mechanism during the transfer process of thin film material in which the thickness increases while continuously moving in air or solution.