• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.9
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• pp.1-10
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• 2011

Unfortunately, in current microprocessors, increasing the frequency causes increased power consumption and reduced reliability whereas it improves the performance. To overcome the power and thermal problems in the singlecore processors, multicore processors has been widely used. For 2D multicore processors, interconnection is regarded as one of the major constraints in performance and power efficiency. To reduce the performance degradation and the power consumption in 2D multicore processors, 3D integrated design technique has been studied by many researchers. Compared to 2D multicore processors, 3D multicore processors get the benefits of performance improvement and reduced power consumption by reducing the wire length significantly. However, 3D multicore processors have serious thermal problems due to high power density, resulting in reliability degradation. Detailed thermal analysis for multicore processors can be useful in designing thermal-aware processors. In this paper, we analyze the impact of workload distribution, distance to the heat sink, and number of stacked dies on the processor temperature. We also analyze the effects of the temperature on overall system performance. Especially, this paper presents the guideline for thermal-aware multicore processor design by analyzing the thermal problems in 2D multicore processors and 3D multicore processors.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.173-180
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• 2006

An airborne radar is an essential aviation electronic system of the aircraft to perform various missions in all weather environments. This paper presents the design, development, and test results of the multi-mode pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRU units, which include ANTU(Antenna Unit), TRU(Tx Rx Unit), RSDU(Radar Signal & Data Processing Unit) and DISU(Display Unit). The developed technologies include the TACCAR processor, planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, DSP based Doppler FFT filtering, adaptive CFAR, IMU, and tracking capability. The design performance of the developed radar system is verified through various helicopter-borne field tests including MTD (Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.2
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• pp.9-22
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• 2004

This paper presents a parallel genetic algorithm for the Multi-disk data allocation problem an NP-complete problem. This problem is to find a method to distribute a Binary Cartesian Product File on disk-arrays to maximize parallel disk I/O accesses. A Sequential Genetic Algorithm(SGA), DAGA, has been proposed and showed the superiority to the other proposed methods, but it has been observed that DAGA consumes considerably lengthy simulation time. In this paper, a parallel version of DAGA(ParaDAGA) is proposed. The ParaDAGA is a 2-dimension torus-based Parallel Genetic Algorithm(PGA) and it is based on a distributed population structure. The ParaDAGA has been implemented on the parallel computer simulated on a single processor platform. Through the simulation, we study the impact of varying ParaDAGA parameters and compare the quality of solution derived by ParaDAGA and DAGA. Comparing the quality of solutions, ParaDAGA is superior to DAGA in all cases of configurations in less simulation time.

• The Journal of the Acoustical Society of Korea
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• v.23 no.1
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• pp.17-23
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• 2004

The mobile radio channel can be simulated as a complex-valued random process with narrow-band spectrum. This paper describes a real-time implementation of that process using a INS320C6414 digital signal processor and XC2VP30 Virtex FPGA. The simulator presented here is not only a comprehensive model of the flat fading but also frequency selective fading mobile channel conditions. To replicate the statistical characteristics of the multipath fading environment with the minimum computational burden, multi-rate techniques are employed to resolve practical problems such as variable sampling rate. The simulator produces accurate and consistent results due to digital implementation. It is very flexible and simple to program for various field conditions in mobile communications with a graphical user interface.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1778-1784
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• 2016

we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.

• Journal of KIISE:Databases
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• v.37 no.5
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• pp.275-284
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• 2010

GPUs are stream processors based on multi-cores, which can process large data with a high speed and a large memory bandwidth. Furthermore, GPUs are less expensive than multi-core CPUs. Recently, usage of GPUs in general purpose computing has been wide spread. The CUDA architecture from Nvidia is one of efforts to help developers use GPUs in their application domains. In this paper, we propose techniques to parallelize a skyline algorithm which uses a simple nested loop structure. In order to employ the CUDA programming model, we apply our optimization techniques to make our skyline algorithm fit into the performance restrictions of the CUDA architecture. According to our experimental results, we improve the original skyline algorithm by 80% with our optimization techniques.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.154-160
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• 2004

In this paper, implementation of active noise curtains using multiple channel adaptive filters is presented. The same numbers of single channel LMS algorithms as control loudspeakers is used instead of a multi-channel LMS algorithm to reduce the computational burden of adaptive filter algorithms. In general, a multi-channel LMS algorithm is usually used in active noise control system. but this algorithm has much more computational complexity. The single channel control techniques have less amount of DSP calculation, compared to multiple channel control techniques. A stabilizing procedure for adaptive IIR filters is also proposed to improve the stability of recursive LMS algorithms. Both experimental results of two control techniques using TMS320VC33 digital signal processor show the similar noise reduction, but the single channel control techniques are more efficient in practical active noise curtain applications

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.117-124
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• 2002

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution because of the strict requirement for the real-time data transmission of the massive SAR data in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath. The designed data link module can be effectively used for the spaceborne and airborne applications which requires to expand the high speed data link capability.