• Journal of Power Electronics
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• v.16 no.4
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• pp.1598-1611
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• 2016

In some special occasions with strict size requirements, such as mine hoists, improving the design accuracy of the forced-air cooling systems of NPC three-level inverters is a key technology for improving the power density and decreasing the volume. First, a fast power-loss calculation method was brought. Its calculation principle introduced in detail, and the computation formulas were deduced. Secondly, the average and dynamic power losses of a 1MW mine hoist acting as the research target were analyzed, and a forced-air cooling system model based on a series of theoretical analyses was designed with the average power loss as a heat source. The simulation analyses proves the accuracy and effectiveness of this cooling system during the unit lifting period. Finally, according to an analysis of the periodic working condition, the maximum power-loss range of a NPC three-level inverter under multi cycle operation was obtained and its dynamic power loss was taken into the optimized cooling system model as a heat source to solve the power device damage caused by instantaneous heat accumulation. The effectiveness and feasibility of the optimization design based on the dynamic power loss calculation of the maximum power-loss range was proved by simulation and experimental results.

• Journal of Power Electronics
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• v.15 no.1
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• pp.96-105
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• 2015

In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.11
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• pp.547-552
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• 2005

This paper describes a pseudo-random carrier PW technique for the power converters. The proposed method generates a new pseudo-random carrier by randomly composing a carrier with fixed frequency and a carrier with opposition phase. To confirm the validity of the proposed method, a single-phase multi-level inverter was implemented and tested. The experimental results show that the output voltage and current harmonics spectra of an inverter have broadening effect of harmonics, as only simple composition of fixed frequency carries.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.120-126
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• 2019

This study proposes a neutral voltage balance control scheme for stable fault-tolerant operation of an active neutral point clamped (ANPC) inverter using carrier-based pulse width modulation. The proposed scheme maintains the neutral voltage balance by reconfiguring the switching combination and modulating the reference output voltage in order to solve the degradation of the output characteristic in the fault tolerant operation due to the fault of the power semiconductor switch constituting the ANPC inverter. The feasibility of the proposed control scheme is confirmed by HIL experiment using RT-BOX.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.5
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• pp.231-237
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• 2005

Many conventional multi-level inverters have detected switching faults by using the over voltage and current. However, fault detection of the switching elements is very difficult because the voltage and current due to each switching fault decrease more than the normal operation. Moreover, the dc-link unbalancing voltage causes a serious problem in the safety and reliability of system when the 3-level inverter faults occur Therefore, this paper proposes the simple fault diagnose method and the neutral-point-voltage control method that can protect the 3-level inverter system from the unbalancing voltage of the do-link capacitors when the faults of switching elements occur in the 3-level inverter that is very efficient in ac motor drives of the high voltage and high power applications. Through experiment results, the validity of the proposed method is demonstrated.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.4
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• pp.334-340
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• 2004

In this paper, an efficient switching pattern to equalize the size of transformer is proposed for a multi-level inverter employing cascaded transformers. It is based on the prior selected harmonic elimination PWM(SHEPWM) method. Because the maximum magnetic flux imposed on each transformer becomes exactly equal each to each, all transformers can be designed with the same size regardless of their position. Therefore, identical full-bridge inverter units can be utilized, thus improving modularity and manufacturability. The fundamental idea of the proposed switching pattern is illustrated and then analyzed theoretically. The validity of the proposed switching strategy is verified by experimental results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.8-13
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• 2005

In this paper discusses single-phase DC-AC Inverter design of reversible power converter that driven by binary combination at different transformer winding ratio by BCD code level. It has a advantage that constructs a control system simply and obtain load current of good quality without filter circuit and free from noise or isolation for lower switching frequency. In this research, study on current type converter and inverter circuit that consist for possibility of AC-DC/DC-AC multi-level reversible converter.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.3 no.2
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• pp.63-68
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• 1989

This paper discussed the Multi-PAM inverter for static power supply design. The controller part composed of one-chip microcomputer obtained control pattern simply. The configuration of termination part was composed of double bridge inverter and three-phase, three-winding transformer. The output waveforms using a controller and transformers synthesized the multi-PAM wave form by a voltage level of 22 steps per one-cycle. The output waveforms using the Low Pass Filter approximated to the sine wave.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.620-624
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• 2004

Th is paper presents a systematical approach to study carrier based PWM techniques (CPWM) in diode-clamped and cascade multilevel inverters by using the proposed multi-modulating pattern method. This method is based on the vector correlation between CPWM and space vector PWM (SVPWM) and applicable to both multilevel inverter topologies. The CPWM technique can be described in a general mathematical equation, and obtain the same outputs similarly as of corresponding SVPWM. Control of the fundamental voltage, vector redundancies and phase redundancies in multilevel inverter can be formulated separately in the CPWM equation. The deduced CPWM can obtain a full vector redundancy control, and fully utilize phase redundancy in a cascade inverter. In the paper, CPWM equations and corresponding algorithm for generating multi-modulating signals will be performed, in which SVPWM attributes will be presented by corresponding controllable factors.

• Journal of Power Electronics
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• v.16 no.1
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• pp.173-181
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• 2016

In this paper, a new technique for harmonic optimization in cascaded H-bridge 7-level inverters is proposed. The suggested strategy is based on minimizing an objective function which simultaneously optimizes the converter utilization and Total Harmonic Distortion (THD). The Switch Utilization Ratio (SUR) is formulized for both the phase and line-line voltages of a 7-level inverter and is considered in the final objective functions. Based upon the SUR formula, utilization ratio enhancement will reduce the value of feeding DC links, which improves the efficiency and lifetime of the circuit components due to lower voltage stresses and losses. In order to achieve more effective solution in different modulation indices, it is assumed that the DC sources can be altered. Experimental validation is presented based on a three-phase 7-level inverter prototype.