• Title/Summary/Keyword: Multi-input converter

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A Study on the Optimization of Offsite Consequence Analysis by Plume Segmentation and Multi-Threading (플룸분할 및 멀티스레딩을 통한 소외사고영향 분석시간 최적화 연구)

  • Seunghwan, Kim;Sung-yeop, Kim
    • Journal of the Korean Society of Safety
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    • v.37 no.6
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    • pp.166-173
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    • 2022
  • A variety of input parameters are taken into consideration while performing a Level 3 PSA. Some parameters related to plume segments, spatial grids, and particle size distribution have flexible input formats. Fine modeling performed by splitting a number of segments or grids may enhance the accuracy of analysis but is time-consuming. Analysis speed is highly important because a considerably large number of calculations is required to handle Level 2 PSA scenarios for a single-unit or multi-unit Level 3 PSA. This study developed a sensitivity analysis supporting interface called MACCSsense to compare the results of the trials of plume segmentation with the results of the base case to determine its impact (in terms of time and accuracy) and to support the development of a modeling approach, which saves calculation time and improves accuracy. MACCSense is an automation tool that uses a large amount of plume segmentation analysis results obtained from MUST Converter and Mr. Manager developed by KAERI to generate a sensitivity report that includes impact (time and accuracy) by comparing them with the base-case result. In this study, various plume segmentation approaches were investigated, and both the accuracy and speed of offsite consequence analysis were evaluated using MACCS as a consequence analysis tool. A simultaneous evaluation revealed that execution time can be reduced using multi-threading. In addition, this study can serve as a framework for the development of a modeling strategy for plume segmentation in order to perform accurate and fast offsite consequence analyses.

Investigation of the IPMSM Parameter Variation Effect to the System Operation Characteristics of the Multi Inverter Driven High Speed Train System (다중 인버터 구동 고속전철 시스템의 IPMSM 파라미터 변동에 따른 운전 특성 고찰)

  • Park, Dong-Kyu;Jin, Kang-Hwan;Chang, Chin-Young;Kim, Sung-Je;Kim, Yoon-Ho
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.60 no.4
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    • pp.193-199
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    • 2011
  • The next generation domestic high speed railway system is a power distributed type and uses vector control method for motor speed control. Nowadays, inverter driven induction motor system is widely used. However, recently PMSM drives are deeply considered as a alternative candidate instead of an induction motor driven system due to their advantages in efficiency, noise reduction and maintenance. The next-generation high-speed train is composed of 2 converter units, 4 inverter units, and 4 Traction Motor units. Each motor is connected to the inverter directly. In this paper, the effects of IPMSM parameter variation to the system operation characteristics of the multi inverter driven high speed train system are investigated. The parallel connected inverter input-output characteristics are analyzed to the parameter mismatches of the IPMSM in 1C1M control using Matlab/Simulink, then the reliability of the simulation results are verified through experimental results.

Three Level Buck Converter Utilizing Multi-bit Flying Capacitor Voltage Control (멀티비트 플라잉 커패시터의 전압제어를 이용한 3-레벨 벅 변환기)

  • So, Jin-Woo;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1006-1011
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    • 2018
  • This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

Control Strategy for Three-Phase Grid-Connected Converters under Unbalanced and Distorted Grid Voltages Using Composite Observers

  • Nguyen, Thanh Hai;Lee, Dong-Choon
    • Journal of Power Electronics
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    • v.13 no.3
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    • pp.469-478
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    • 2013
  • This paper proposes a novel scheme for the current controller for the grid-side converter (GSC) of permanent-magnet synchronous generator (PMSG) wind turbines to eliminate the high-order harmonics in the grid currents under grid voltage disturbances. The voltage unbalance and harmonics in three-phase systems cause grid current distortions. In order to mitigate the input current distortions, multi-loop current controllers are applied, where the positive-sequence component is regulated by proportional-integral (PI) controllers, and the negative-sequence and high-order harmonic components are regulated by proportional-resonance (PR) controllers. For extracting the positive/negative-sequence and harmonic components of the grid voltages and currents without a phase delay or magnitude reduction, composite observers are applied, which give faster and more precise estimation results. In addition, an active damping method using PR controllers to damp the grid current component of the resonant frequency is employed to improve the operating stability of VSCs with inductor-capacitor-inductor (LCL) filters. The validity of the proposed method is verified by simulation and experimental results.

Design of a 26ps, 8bit Gated-Ring Oscillator Time-to-Digital Converter using Vernier Delay Line (버니어 지연단을 이용한 26ps, 8비트 게이티드 링 오실레이터 시간-디지털 변환기의 설계)

  • Jin, Hyun-Bae;Park, Hyung-Min;Kim, Tae-Ho;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.7-13
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    • 2011
  • This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

Developed power supply for small Millimeterwave(Ka band) radar (소형 밀리미터파(Ka 밴드) 레이다용 전원공급기 개발)

  • Kim, Hong-Rak;Woo, Seon-Keol;Lee, Young-Soo;Kim, Youn-Jin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.1
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    • pp.197-202
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    • 2019
  • A small millimeter-wave tracking radar power supply must provide stable power with minimal ripple noise and the switching frequency noise of the DC-DC converter must have a real-time self-test capability through on-the-fly monitoring without causing false alarms and ghost In this study, we developed a multi-output switching power supply with output power of more than 80% (@ 100% load) and 10 output power by adopting + 28VDC input for application to small millimeter wave tracking radar, DC-DC converter is applied for large power output and multi-output flyback method is applied for the remaining small power output. The test results show that 85% efficiency efficiency is achieved under 100% load condition.

Structure and Control of Smart Transformer with Single-Phase Three-Level H-Bridge Cascade Converter for Railway Traction System (Three-Level H-Bridge 컨버터를 이용한 철도차량용 지능형 변압기의 구조 및 제어)

  • Kim, Sungmin;Lee, Seung-Hwan;Kim, Myung-Yong
    • Journal of the Korean Society for Railway
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    • v.19 no.5
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    • pp.617-628
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    • 2016
  • This paper proposes the structure of a smart transformer to improve the performance of the 60Hz main power transformer for rolling stock. The proposed smart transformer is a kind of solid state transformer that consists of semiconductor switching devices and high frequency transformers. This smart transformer would have smaller size than the conventional 60Hz main transformer for rolling stock, making it possible to operate AC electrified track efficiently by power factor control. The proposed structure employs a cascade H-Bridge converter to interface with the high voltage AC single phase grid as the rectifier part. Each H-Bridge converter in the rectifier part is connected by a Dual-Active-Bridge (DAB) converter to generate an isolated low voltage DC output source of the system. Because the AC voltage in the train system is a kind of medium voltage, the number of the modules would be several tens. To control the entire smart transformer, the inner DC voltage of the modules, the AC input current, and the output DC voltage must be controlled instantaneously. In this paper, a control algorithm to operate the proposed structure is suggested and confirmed through computer simulation.

Discriminant Analysis of Marketed Liquor by a Multi-channel Taste Evaluation System

  • Kim, Nam-Soo
    • Food Science and Biotechnology
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    • v.14 no.4
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    • pp.554-557
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    • 2005
  • As a device for taste sensation, an 8-channel taste evaluation system was prepared and applied for discriminant analysis of marketed liquor. The biomimetic polymer membranes for the system were prepared through a casting procedure by employing polyvinyl chloride, bis (2-ethylhexyl)sebacate as plasticizer and electroactive materials such as valinomycin in the ratio of 33:66:1, and were separately attached over the sensitive area of ion-selective electrodes to construct the corresponding taste sensor array. The sensor array in conjunction with a double junction reference electrode was connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a personal computer via an A/D converter. When the signal data from the sensor array for 3 groups of marketed liquor like Maesilju, Soju and beer were analyzed by principal component analysis after normalization, it was observed that the 1st, 2nd and 3rd principal component were responsible for most of the total data variance, and the analyzed liquor samples were discriminated well in 2 dimensional principal component planes composed of the 1st-2nd and the 1st-3rd principal component.

Operation Characteristics Investigation of the Next Generation High Speed Railway System with respect to IPMSM Parameter Variation (IPMSM 파라미터 변동에 따른 차세대 고속전철 시스템의 운전 특성 고찰)

  • Park, Dong-Kyu;Suh, Yong-Hun;Lee, Sang-Hyun;Jin, Kang-Hwan;Kim, Yoon-Ho
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.3133-3141
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    • 2011
  • The next generation domestic high speed railway system is a power distributed type and uses vector control method for motor speed control. Nowadays, inverter driven induction motor system is widely used. However, recently PMSM drives are deeply considered as a alternative candidate instead of an induction motor drive system due to their advantages in efficiency, noise reduction and maintenance. The next-generation high speed train is composed of 2 converter units, 4 inverter units, and 4 Traction Motor units. Each motor is connected to the inverter directly. In this paper, the effect of IPMSM parameter variations to the system operation characteristics of the multi inverter drive high speed train system are investigated. The parallel connected inverter input-output characteristics are analyzed to the parameter mismatches of IPMSM using the 1C1M control simulator based on Matlab/Simulink.

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Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

  • Lee, Kwang-Jin;Kim, Tae-Hyoung;Cho, Uk-Rae;Byun, Hyun-Geun;Kim, Su-Ki
    • ETRI Journal
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    • v.27 no.1
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    • pp.81-88
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    • 2005
  • In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

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