• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.116.2-116.2
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• 2013

최근 그래핀, hexagonal boron nitride (h-BN) 및 $MoS_2$ (molybdenum disulfide)와 같은 2차원 결정 물질들은 무어의 법칙 (Moore's Law)를 뛰어넘어 계속적인 소자의 소형화를 가능케 하고 또한 대면적, 저비용 소자 개발을 가능케 하는 우수한 특성을 가진 차세대 반도체 트랜지스터 소재로 각광받고 있다. $MoS_2$는 bulk 상태일 때는 1.2 eV의 indirect 밴드갭을 가지지만 단층형태일 때는 1.8 eV의 direct 밴드갭을 가지며 dielectric screening 기법 등을 통해 mobility를 향상시킬 수 있는 것으로 연구된 바 있다. 본 연구에서는 화학기상증착(chemical vapor deposition, CVD)법을 이용하여 $MoS_2$박막을 형성하기 위한 기초연구인 Mo전구체의 특성 평가 및 적합한 공정조건 개발 연구를 수행하였다. 사용한 전구체는 $Mo(CO)^6$ (Molybdenum hexacarbonyl)이고, 온도 및 압력, 반응기체($H_2S$, Hydrogen sulfide) 유량 등의 공정 조건 변화에 따른 거동을 Fourier transform infrared spectroscopy (FT-IR) 시스템을 사용하여 측정하였다. 또한 $Mo(CO)^6$의 분자구조를 상용 프로그램인 Gaussian으로 시뮬레이션 하여 실제 FT-IR 측정 결과값과 비교 분석하였다. 화학기상증착법을 이용한 $MoS_2$ 증착조건 최적화를 위하여 다양한 온도, 유량, 압력, 및 기판 종류에 대하여 증착 실험을 수행하였으며, 증착된 샘플은 scanning electron microscope (SEM), Raman spectroscopy를 이용하여 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.252-252
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• 2013

최근 그래핀, hexagonal boron nitride (h-BN) 및 $MoS_2$ (molybdenum disulfide)와 같은 2차원 결정 물질들은 무어의 법칙(Moore's Law)를 뛰어넘어 계속적인 소자의 소형화를 가능케 하고 또한 대면적, 저비용 소자 개발을 가능케 하는 우수한 특성을 가진 차세대 반도체 트랜지스터 소재로 각광받고 있다. $MoS_2$는 bulk 상태일 때는 1.2 eV의 indirect 밴드갭을 가지지만 단층형태일 때는 1.8 eV의 direct 밴드갭을 가지며 dielectric screening 기법등을 통해 mobility를 향상시킬 수 있는 것으로 연구된 바 있다. 본 연구에서는 화학기상증착 (chemical vapor deposition)법을 이용하여 $MoS_2$ 박막을 형성하기 위한 기초연구인 Mo 전구체의 특성평가 및 적합한 공정조건 개발 연구를 수행하였다. 사용한 전구체는 $Mo(CO)_6$ (Molybdenum hexacarbonyl)이고, 온도 및 압력, 반응기체(H2 S, Hydrogen sulfide) 유량 등의 공정 조건 변화에 따른 거동을 Fourier transform infrared spectroscopy (FT-IR) 시스템을 사용하여 측정하였다. 또한 $Mo(CO)_6$의 분자구조를 상용 프로그램인 Gaussian으로 시뮬레이션 하여 실제 FT-IR 측정 결과값과 비교 분석하였다.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.37-52
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• 2013

무어의 법칙에 따르면, 반도체의 집적도 2년마다 2배씩 증가한다고 한다. 무어의 법칙은 지금까지는 집적회로 기술의 발전을 잘 예측했다. 하지만 트랜지스터의 사이즈를 줄일수록 누수전류와 회로의 저항을 조절하기 어렵기 때문에 트랜지스터의 소형화에는 한계가 있다. 우리는 곧 무어의 법칙의 한계를 맞이할 것이다. 그래서 트랜지스터를 더욱 소형화시키기 위해서는 bottom-up analysis가 필요한 시점이다. Top-down analysis가 초기의 커다란 트랜지스터에서 점점 소형화를 시켜 작은 트랜지스터를 만든다는 개념인 반면, Bottom-up analysis는 처음부터 작은 분자를 조작하여 트랜지스터와 같은 성질을 띄도록 만드는 개념이다. 분자가 기억소자로서 이용되려면 저항이 다른 2가지 안정한 상태가 필요하다. 이번 연구에서 나는 기억소자를 디자인 하기 위하여 high spin state와 low spin state 두 가지 안정한 상태를 가지는 spin crossover complex를 이용하기로 했다. 이전의 연구에서 spin crossover 는 전기장을 이용해서도 유도될 수 있다고 확신하였고, 이를 이용해서 기억소자를 디자인하기로 하였다. 이번 연구를 위해서 symmetry를 가지는 octahedral spin crossover complex를 디자인하였고 이를 '기억 분자'라고 명명했다. 그리고 이 분자의 high spin state와 low spin state가 전기장을 이용하여 서로 바뀔 수 있는지 가능성을 DFT with B3LYP functional을 이용해서 비교했다. 그 결과로 전기장을 이용하여 기억분자의 spin crossover을 일으킬 수는 있지만 abnormally strong electric field를 써야 한다는 사실을 알아냈다. 이번 연구를 토대로 추후의 연구를 위해, 기억소자가 되기 위하여 분자가 어떤 특징을 만족시켜야 하는지를 분석했다.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• Genomics & Informatics
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• v.12 no.1
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• pp.2-11
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• 2014

After the initial enthusiasm of the human genome project, it became clear that without additional data pertaining to the epigenome, i.e., how the genome is marked at specific developmental periods, in different tissues, as well as across individuals and species-the promise of the genome sequencing project in understanding biology cannot be fulfilled. This realization prompted several large-scale efforts to map the epigenome, most notably the Encyclopedia of DNA Elements (ENCODE) project. While there is essentially a single genome in an individual, there are hundreds of epigenomes, corresponding to various types of epigenomic marks at different developmental times and in multiple tissue types. Unprecedented advances in next-generation sequencing (NGS) technologies, by virtue of low cost and high speeds that continue to improve at a rate beyond what is anticipated by Moore's law for computer hardware technologies, have revolutionized molecular biology and genetics research, and have in turn prompted innovative ways to reduce the problem of measuring cellular events involving DNA or RNA into a sequencing problem. In this article, we provide a brief overview of the epigenome, the various types of epigenomic data afforded by NGS, and some of the novel discoveries yielded by the epigenomics projects. We also provide ample references for the reader to get in-depth information on these topics.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.