• Title/Summary/Keyword: Montgomery modular multiplication

Search Result 50, Processing Time 0.024 seconds

Hardware Design of Efficient Montgomery Multiplier for Low Area RSA (저면적 RSA를 위한 효율적인 Montgomery 곱셈기 하드웨어 설계)

  • Nti, Richard B.;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2017.10a
    • /
    • pp.575-577
    • /
    • 2017
  • In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

  • PDF

Implementation of 2,048-bit RSA Based on RNS(Residue Number Systems) (RNS(Residue Number Systems) 기반의 2,048 비트 RSA 설계)

  • 권택원;최준림
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.4
    • /
    • pp.57-66
    • /
    • 2004
  • This paper proposes the design of a 2,048-bit RSA based on RNS(residue number systems) Montgomery modular multiplier As the systems that RNS processes a fast parallel modular multiplication for a large word partitioned into small words, we introduce Montgomery reduction method(MRM)[1]based on Wallace tree modular multiplier and 33 RNS bases with 64-bit size for RNS Montgomery modular multiplication in this paper. Also, for fast RNS modular multiplication, a modified method based on Chinese remainder theorem(CRT)[2] is presented. We have verified 2,048-bit RSA based on RNS using Samsung 0.35${\mu}{\textrm}{m}$ technology and the 2,048-bit RSA is performed in 2.54㎳ at 100MHz.

A Study on FPGA Implementation of Radix-16 Montgomery Modular Multiplication and Comparison of Power Dissipation (Radix-16 Montgomery Modular 곱셈 알고리즘의 FPGA 구현과 전력 소모 비교에 관한 연구)

  • Kim, Pan-Ki;Kim, Ki-Young;Kim, Seok-Yoon
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.813-816
    • /
    • 2005
  • In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.

  • PDF

The Montgomery Multiplier Using Scalable Carry Save Adder (분할형 CSA를 이용한 Montgomery 곱셈기)

  • 하재철;문상재
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.10 no.3
    • /
    • pp.77-83
    • /
    • 2000
  • This paper presents a new modular multiplier for Montgomery multiplication using iterative small carry save adder. The proposed multiplier is more flexible and suitable for long bit multiplication due to its scalable property according to design area and required computing time. We describe the word-based Montgomery algorithm and design architecture of the multiplier. Our analysis and simulation show that the proposed multiplier provides area/time tradeoffs in limited design area such as IC cards.

Design of RSA cryptographic circuit for small chip area using refined Montgomery algorithm (개선된 몽고메리 알고리즘을 이용한 저면적용 RSA 암호 회로 설계)

  • 김무섭;최용제;김호원;정교일
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.12 no.5
    • /
    • pp.95-105
    • /
    • 2002
  • This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.

Study on High-Radix Montgomery's Algorithm Using Operand Scanning Method (오퍼랜드 스캐닝 방법을 이용한 다진법 몽고메리 알고리즘에 대한 연구)

  • Moon, San-Gook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2008.10a
    • /
    • pp.732-735
    • /
    • 2008
  • In order for fast calculation for the modular multiplication which plays an essential role in RSA cryptography algorithm, the Montgomery algorithm has been studed and developed in varous ways. Since there is no division operation in the algorithm, it is able to perform a fast modular multiplication. However, the Montgomery algorithm requires a few extra operations in the progress of which transformation from/to ordinary modular form to/from Montgomery form should be made. Concept of high radix operation can be considered by splitting the key size into word-defined units in the RSA cryptosystems which use longer than 1024 key bits. In this paper, We adopted the concept of operand scanning methods to enhance the traditional Montgomery algorithm. The methods consider issues of optimization, memory usage, and calculation time.

  • PDF

FPGA Implementation of High Speed RSA Cryptosystem Using Radix-4 Modified Booth Algorithm and CSA (Radix-4 Modified Booth 알고리즘과 CSA를 이용한 고속 RSA 암호시스템의 FPGA 구현)

  • 박진영;서영호;김동욱
    • Proceedings of the IEEK Conference
    • /
    • 2001.06a
    • /
    • pp.337-340
    • /
    • 2001
  • This paper presented a new structure of RSA cryptosystem using modified Montgomery algorithm and CSA(Carry Save Adder) tree. Montgomery algorithm was modified to a radix-4 modified Booth algorithm. By appling radix-4 modified Booth algorithm and CSA tree to modular multiplication, a clock cycle for modular multiplication has been reduced to (n+3)/2 and carry propagation has been removed from the cell structure of modular multiplier. That is, the connection efficiency of full adders is enhanced.

  • PDF

Montgomery Multiplier Supporting Dual-Field Modular Multiplication (듀얼 필드 모듈러 곱셈을 지원하는 몽고메리 곱셈기)

  • Kim, Dong-Seong;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.24 no.6
    • /
    • pp.736-743
    • /
    • 2020
  • Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

Study of Modular Multiplication Methods for Embedded Processors

  • Seo, Hwajeong;Kim, Howon
    • Journal of information and communication convergence engineering
    • /
    • v.12 no.3
    • /
    • pp.145-153
    • /
    • 2014
  • The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

Bit-sliced Modular Multiplication Algorithm and Implementation (비트 확장성을 갖는 모듈러 곱셈 알고리즘 및 모듈러 곱셈기 설계)

  • 류동렬
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.10 no.3
    • /
    • pp.3-10
    • /
    • 2000
  • In this paper we propose a bit-sliced modular multiplication algorithm and a bit-sliced modular multiplier design meeting the increasing crypto-key size for RSA public key cryptosystem. The proposed bit-sliced modular multiplication algorithm was designed by modifying the Montgomery's algorithm. The bit-sliced modular multiplier is easy to expand to process large size operands and can be immediately applied to RSA public key cryptosystem.