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http://dx.doi.org/10.13089/JKIISC.2002.12.5.95

Design of RSA cryptographic circuit for small chip area using refined Montgomery algorithm  

김무섭 (한국전자통신연구원 정보보호기술연구본부)
최용제 (한국전자통신연구원 정보보호기술연구본부)
김호원 (한국전자통신연구원 정보보호기술연구본부)
정교일 (한국전자통신연구원 정보보호기술연구본부)
Abstract
This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.
Keywords
RSA; Montgomery algorithm; Modular multiplication; Modular exponential;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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