• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.6
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• pp.1071-1079
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• 2010

This paper describes the design and fabrication of a high-efficiency GaN HEMT(Gallium Nitride High-electron Mobility Transistor) Pallet power amplifier module for S-band phased array radar applications. Pallet amplifier module has a series 2-cascaded power amplifier and the final amplification-stage consists of balanced GaN HEMT transistor. In order to achieve high efficiency characteristic of pallet power amplifier module, all amplifiers are designed to the switching-mode amplifier. We performed with various PRF(Pulse Repetition Frequency) of 1, 10, 100 and 1000Hz at a fixed pulse width of $100{\mu}s$. In the experimental results, the output power, gain, and drain efficiency(${\eta}_{total}$) of the Pallet power amplifier module are 300W, 33dB, and 51% at saturated output power of 2.9GHz, respectively.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.81-85
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• 2012

This paper presents a wideband and low-noise direct conversion front-end receiver supporting VHF and UHFbands simultaneously. The receiver iscomposed of a low-noise amplifier (LNA), a down conversion quadrature mixer, and a frequency divider by 2. The cascode configuration with the resistor feedback is exploited in the LNA to achieve a wide operating bandwidth. Four gainstep modesare employed using a switched resistor bank and a capacitor bank in the signal path to cope with wide dynamic input power range. The verticalbipolar junction transistors are used as the switching elements in the mixer to reduce 1/f noise corner frequency. The proposed front-end receiver fabricated in 0.18 ${\mu}m$ CMOS technology shows very low minimum noise figureof 1.8 dB and third order input intercept pointof -12dBm inthe high-gain mode of 26.5 dBmeasured at 500 MHz.The proposed receiverconsumeslow current of 20 mA from a 1.8 V power supply.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.800-811
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• 2018

This paper presents a regenerative braking control scheme for Switched Reluctance Machine (SRM) drive in Electric Vehicles (EVs). The main purpose is to maximize the recovered energy during battery charging by taking into account the nonlinear physical characteristics of the Switched Reluctance Machine. The proposed regenerative braking method employs the back-EMF in the generation process as a complicated position-dependent voltage source. The proposed maximum power recovery (MPR) operation of the regenerative braking is first based on the maximization of the extracted power from the machine and then the maximization of the power transferred to the battery. The maximum power extraction (MPE) from SRM is based on maximizing the energy conversion ratio by the calculation of the optimum PWM switching duty cycle, turn-on, and turn-off angles. By using the impedance matching theorem that allows the maximum power transfer (MPT) of the MPE, the proposed MPR is achieved. The parametric averaged value modeling of the machine phase currents in the chopping control mode is used for MPR realization. By following this model, a nonlinear equivalent input resistance is derived for the battery internal resistance matching. The effectiveness of the proposed regenerative braking method is demonstrated through simulation results and experimental implementation.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.452-455
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• 2005

This paper proposes a new sustaining driver for AC PDP(Plasma Display Panel), which improves the performance of conventional circuit with reduced sustain voltage such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver and there is no energy recovery circuit. The circuit proposed in his paper has an energy recovery circuit and removes surge currents. Although the energy recovery circuit is added, the number of active switching elements is the same as the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations using PSpice program.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1200-1208
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• 2016

Planar electromagnetic interference (EMI) filter has significant engineering significance to power electronic system integration and miniaturization. However, the value of differential mode capacitance cannot meet the demand of noise suppression because of the size limit of ceramics. In this case, the EMI filter of novel multilayers is recommended to address this issue. A novel integrated structure of EMI filter based on multilayer ceramic is proposed in this study. The inductance and capacitance of the new structure can be designed separately, which is an advantage in manufacturing. Insertion loss is measured more closely to the actual situation in this study, which is different from the condition where source and load impedances are both 50 Ω. In the process of designing a novel EMI filter, noise impedance is considered. Moreover, the prototype is created and applied to a small switching power supply, which verifies the effectiveness of the developed EMI filter.

• Journal of Power Electronics
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• v.11 no.6
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• pp.914-921
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• 2011

Commencing with incandescent light bulbs, every load today creates harmonics. Unfortunately, these loads vary with respect to their amount of harmonic content and their response to problems caused by harmonics. The prevalent difficulties with harmonics are voltage and current waveform distortions. In addition, Electronic equipment like computers, battery chargers, electronic ballasts, variable frequency drives, and switching mode power supplies generate perilous amounts of harmonics. Issues related to harmonics are of a greater concern to engineers and building designers because they do more than just distort voltage waveforms, they can overheat the building wiring, cause nuisance tripping, overheat transformer units, and cause random end-user equipment failures. Thus power quality is becoming more and more serious with each passing day. As a result, active power filters (APFs) have gained a lot of attention due to their excellent harmonic compensation. However, the performance of the active filters seems to have contradictions with different control techniques. The main objective of this paper is to analyze shunt active filters with fuzzy and pi controllers. To carry out this analysis, active and reactive current methods ($i_d-i_q$) are considered. Extensive simulations were carried out. The simulations were performed under balance, unbalanced and non sinusoidal conditions. The results validate the dynamic behavior of fuzzy logic controllers over PI controllers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2515-2518
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• 2008

The vacuum interrupter (VI) is widely used in medium-voltage switching circuits due to its abilities and advantages as an environmental friendly circuit breaker. An understanding of the vacuum arc flow phenomena is very important for improving the performance of vacuum interrupter. In order to closely examine the vacuum arc phenomena, it is necessary to predict the magnetohydrodynamic (MHD) characteristics by the multidisciplinary numerical modeling, which is coupled with the electromagnetic and the thermal flow fields, simultaneously. In this study, we have investigated arc plasma constriction phenomena and an effect of AMF on the arc plasma with the high-current vacuum arcs for the cup-type AMF electrode by using a commercial finite element analysis (FEA) package, ANSYS. The simulation results applied with various AMFs and constant Joule heat generation show that strong axial magnetic field (AMF) permits the arc to be maintained in a diffused mode to a high-current vacuum arc. However, further studies are required on the two-way coupling method and radiation model for arc plasma in order to accomplish the advanced analysis method.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.