• Journal of Korea Multimedia Society
• /
• v.11 no.2
• /
• pp.163-174
• /
• 2008

The H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. However, to achieve such high coding efficiency, the complexity of H.264/AVC encoder is also increased drastically than previous ones, mainly because of mode decision. In this paper, we propose a three-step mode decision algorithm for fast encoding in H.264/AVC. In the first step, we select skip mode or inter mode by considering the temporal correlation and spatial correlation. In the second step, if the result of the first step is INTER mode, we select one group between two groups for final mode. In the third step, we select final mode by exploiting the pixel values of error macroblock or the modes of adjacent macroblocks. Simulations show that the proposed method reduces the encoding time by 42% on average without any significant PSNR losses.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2002.05a
• /
• pp.549-553
• /
• 2002

Although the magnetostrictive sensors have received much attention in recent years. the investigations on the selection of a desired mode have not been reported. The purpose of this investigation is to present a technique to select a desired mode in a solid ferromagnetic cylinder using a non-contact magnetostrictive sensor. To achieve this goal. we propose new bias magnet configurations to select longitudinal and flexural waves. A few experimental results confirm the validity of the present investigation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.205-210
• /
• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.3
• /
• pp.39-46
• /
• 1994

CMOS LCD driving circuits using poly-Si TFT have been designed and basic blocks including test patterns have been fabricated. Column driver drives the pixels by block because polu-Si TFT can not operate at the speed of video signal. Row driver has mode selection circuit which can select a mode between interlacing mode and non-interlacing mode. Experimental results show shift register can operate at 1MHz colck frequency with 4pF load.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4C
• /
• pp.321-329
• /
• 2008

H.264/AVC video coding standard enables a considerably higher improvement in coding efficiency compared with previous standards such as MPEG-2, H.263 and MPEG-4. To achieve this, for each macro-block in H.264/AVC, Rate-Distortion Optimization (RDO) technique is employed to select the best motion vector, reference frame, and macro-block mode. As a result, computational complexity is increased significantly whereas RDO achieve higher improvement. This paper presents fast intra mode selection algorithm based on constraints of frequency characteristics which are derived from intra coding modes of H.264/AVC. First of all, we observe the features of each intra mode through the frequency analysis of image. And then proposed Frequency Error Costs (FECs) are calculated to select the best mode which has minimum cost. Computational complexity is considerably reduced because rate-distortion costs only calculate the candidate modes which are set of best mode and its neighbouring two modes. Experimental results show that proposed algorithm reduces the complexity dramatically maintaining the rate-distortion performance compared with H.264/AVC reference software.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.1
• /
• pp.6-14
• /
• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.51-51
• /
• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Structural Engineering and Mechanics
• /
• v.39 no.6
• /
• pp.813-831
• /
• 2011

This paper presents an efficient version of Hilbert-Huang transform for nonlinear non-stationary systems analyses. An ensemble empirical mode decomposition (EEMD) is introduced to alleviate the problem of mode mixing between intrinsic mode functions (IMFs) decomposed by EMD. Yet the problem has not been fully resolved when a signal of a similar scale resides in different IMF components. Instead of using a trial and error method to select the "best" outcome generated by EEMD, a hybrid algorithm based on EEMD and EMD is proposed for multi-mode signal processing. The developed approach comprises the steps from a bandpass filter design for regrouping modes of the IMFs obtained from EEMD, to the mode extraction using EMD, and to the assessment of each mode in the marginal spectrum. A simulated two-mode signal is tested to demonstrate the efficiency and robustness of the approach, showing average relative errors all equal to 1.46% for various noise levels added to the signal. The developed approach is also applied to a real bridge structure, showing more reliable results than the pure EMD. Discussions on the mode determination are offered to explain the connection between modegrouping form on the one hand, and mode-grouping performance on the other.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.50-52
• /
• 2003

This paper presents characteristics analysis of brushless DC motor(BLDCM) which driven by two types of PWM mode. The phase current and torque ripples are generated differently at each PWM mode. So they have a different influence on motor characteristics. In this paper, we have analyzed characteristics of BLDCM using time-stepped voltage source finite element method. The effect of two types of PWM mode had been confirmed by comparing each phase current and torque ripple waveform. The compared simulation result is useful to select a better PWM mode.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.5
• /
• pp.94-102
• /
• 1998

In this paper, we proposed a dynamic selection scheme of advnaced prediction mode(DAPM), which reduces computational cost and improves coding efficiency. We can select the mode between default prediction mode (DPM) and advanced prediction mode (APM) according to motion componenets in a frame dynamically. For this purpose, we defined error distribution of motion estimation (EDME) as sum of absolute difference(SAD) for each searching points. This distribution region is divided to four subregions. We calculate minimum values in each subregions and then, we determine whether block motion estimation is performed or not depending on the results. As a result, we reduced computational complexity to 30% without degradation of image quality compared to fixed APM(FAPM) by selecting DPM for linear movement.