• 대한전자공학회논문지SD
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• 제47권3호
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• pp.18-27
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• 2010

본 논문에서는 offset self-calibration 기법을 적용한 7-bit 1GSPS folding-interpolation A/D 변환기를 제안한다. 제안하는 A/D 변환기는 folding rate 2, interpolation rate 8의 1+6 구조로 고속 동작에 적합하게 설계되었다. 또한 offset self-calibration 회로를 설계하여 공정 mismatch, 기생 저항, 기생 캐패시턴스 등에 의한 offset-voltage의 변화를 감소시켜 A/D 변환기의 성능 특성을 향상 시켰다. 제안하는 A/D 변환기는 1.2V 65nm 1-poly 6-metal CMOS 공정을 사용하여 설계 되었으며 유효 칩 면적은 $0.87mm^2$, 1.2V 전원전압에서 약 110mW의 전력소모를 나타내었다. 측정 결과 샘플링 주파수 800MHz, 입력 주파수 250MHz에서 39.1dB의 SNDR 특성을 보여주었으며, offset self-calibration 회로를 사용 하지 않은 A/D 변환기에 비해 SNDR이 약 3 dB 향상되었다.

• Journal of Positioning, Navigation, and Timing
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• 제6권2호
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• pp.43-51
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• 2017

In this study, the effect of the steering vector model mismatch due to array uncertainties on the performance of array processing was analyzed through simulation, along with the alleviation of the model mismatch effect depending on array calibration. To increase the reliability of the simulation results, the actual steering vector of the array antenna obtained by electromagnetic simulation was used along with the Jahn's channel model, which is an experimental channel model. Based on the analysis of the power spectrum for each direction, beam pattern, and the signal-to-interference-plus-noise ratio of the beamformer output, the performance deterioration of array processing due to array uncertainties was examined, and the performance improvement of array processing through array calibration was also examined.

• 대한전자공학회논문지SD
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• 제48권4호
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• pp.14-23
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• 2011

본 논문에서는 자체보정 벡터 발생기(Self-Calibrated Vector Generator)를 이용한 7-bit 2GSPS folding/interpolation A/D Converter (ADC)를 제안한다. 제안하는 ADC는 2GSPS 의 고속 변환에 적합한 상위 2-bit, 하위 5-bit 인 분할구조로 설계 되었으며, 각각의 folding/interpolation rate는 4와 8로 설정되었다. 최대 1GHz의 높은 입력신호를 처리하기 위해 cascade 구조의 preprocessing block을 적용하였으며, 전압 구동 방식 interpolation 기법을 적용하여 기준전압 생성 시 발생하는 추가적인 전력소모를 최소화하였다. 또한, 새로운 개념의 자체보정 벡터 발생기를 이용하여 device mismatch, 기생 저항 및 커패시턴스 등에 의한 offset error를 최소화하였다. 제안하는 ADC는 1.2V 0.13um 1-poly 7-metal CMOS 공정을 사용하여 설계 되었으며 calibration 회로를 포함한 유효 칩 면적은 2.5$mm^2$ 이다. 측정 결과 입력 주파수 9MHz, sampling 주파수 2GHz에서 39.49dB의 SNDR 특성을 보이며, calibration 회로의 작동결과 약 3dB 정도의 SNDR의 상승을 확인하였다.

• 한국기계가공학회지
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• 제13권6호
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• pp.139-144
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• 2014

As a result of a mismatch of the residual stress between both sides of the silicon wafer, which warps and distorts during the patterning process. The accuracy of the warpage measurement is related to the calibration. A CCD camera was used for the calibration. Performing optimization of the error function constructed with phase values measured at each pixel on the CCD camera, the coordinates of each light source can be precisely determined. Measurement results after calibration was performed to determine the warpage of the silicon wafer demonstrate that the maximum discrepancy is $5.6{\mu}m$ with a standard deviation of $1.5{\mu}m$ in comparison with the test results obtained by using a Form TalySurf instrument.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1568-1572
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• 2004

This paper proposes a new online calibration algorithm for the array antenna system. As you know, the several previous calibration methods for the mutual coupling did not estimate but measure mutual coupling effect at the real or test-bed system directly. Therefore we suggest some idea to compensate the calibration errors due to mutual coupling effect and mismatch in cables and electronic modules without the off-line calibration. In this work, we can calibrate the array antenna system under the operation of the system using Independent Component Analysis(ICA). This is what is called an online calibration. As you know, the ICA method has permutation and scaling problems. However, we solve problems of the ICA method and apply it to the calibration of an array antenna. The method simultaneously estimates the DOA(Direction of Arrival) of the signals, and calibrates the array for that specific angle. The proposed algorithm is evaluated by computer simulation and its behavior is illustrated by a numerical example.

• 한국인쇄학회:학술대회논문집
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• 한국인쇄학회 2000년도 추계학술발표회 논문집
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• pp.0.2-0
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• 2000

Most important step for the color matching in scanner is the color coordinate transformation from the scanner RGB space to device independent uniform color space. A variety of color calibration technologies have been developed for input device. Linear or nonlinear matrices have been conveniently applied to correct the color filter\`s mismatch with color matching function in scanners. The color matching accuracy is expected to be further improved when the nonlinear matrices are optimized into subdivided smaller color spaces than in single matrix of the entire color space. This article proposed the scanner calibration method using subspace division regression analysis and it were compared with conventional method.

• 한국인쇄학회지
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• 제19권1호
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• pp.4-16
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• 2001

Most important step for the color matching in scanner is the color coordinate transformation from the scanner RGB space to device independent uniform color space. A variety of color calibration technologies have been developed for input device. Linear or nonlinear matrices have been conveniently applied to correct the color filter's mismatch with color matching function in scanners. The color matching accuracy is expected to be further improved when the nonlinear matrices are optimized into subdivided smaller color spaces than in single matrix of the entire color space. This article proposed the scanner calibration method using subspace division regression analysis and it were compared with conventional method.

• Journal of electromagnetic engineering and science
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• 제4권2호
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• pp.79-86
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• 2004

In this paper, the uncertainty in the calibration of coaxial thermal noise sources using a noise figure measuring (NFM) equipment is evaluated. Contributions to the uncertainty such as the calibration uncertainty of the standard noise source, mismatch, measurement of adapter efficiency, ambient temperature variation, and repeatability are evaluated in the frequency range of 10 MHz to 18 ㎓. Results show that the expanded uncertainty(k=2) is 0.23 ㏈ for the noise sources of 5 ㏈ and 15 ㏈ ENR, and 0.27 ㏈ for those of 21 ㏈.

• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of Positioning, Navigation, and Timing
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• 제5권1호
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• pp.37-45
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• 2016

In this paper, design and implementation issues for a network-oriented RF emitter localization system with array antenna are discussed. For hardware, the problem of array mismatch and RF/IF channel mismatch are introduced and the calibration schemes for solving those problems are also provided. For software, it is explained how to overcome the drawback of conventional MUltiple Signal Identification and Classification (MUSIC) algorithm in a point of identifying the number of received signals and problems such as Data Association Problem and Ghost Node Problem in regard to multiple emitter localization are presented with some approaches for getting around those problems. Finally, for implementation, a criterion for arranging each of sensors and a requirement for alignment of array antenna' orientation are also given.