• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.13-17
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• 2014

The direct-patternable $SnO_2$ thin film was successfully fabricated by photochemical metal-organic deposition. The composition and chemical bonding state of $SnO_2$ thin film were analyzed by using X-ray photoelectron spectroscopy (XPS) from the surface to the interface with Si substrate. XPS depth profiling analysis allowed the determination of the atomic composition in $SnO_2$ film as a function of depth through the evolution of four elements of C 1s, Si 2p, Sn 3d, and O 1s core level peaks. At the top surface, nearly stoichiometric $SnO_2$ composition (O/Sn ratio is 1.92.) was observed due to surface oxidation but deficiency of oxygen was increased to the interface of patterned $SnO_2/Si$ substrate where the O/Sn ratio was about 1.73~1.75 at the films. This O deficient state of the film may act as an n-type semiconductor and allow $SnO_2$ to be applied as a transparent electrode in optoelectronic applications.

• Advances in nano research
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• 제2권3호
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• pp.173-177
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• 2014

This study is aimed to the numerical modeling of the surface plasmon-polariton excitation by a layer of active (electrically pumped) quantum dots embedded in a semiconductor, covered with a metal. It is shown that this excitation becomes much more efficient if the metal has a form of a thin (with thickness of several nanometers) film. The cause of this enhancement in comparison with a thick covering metal film is the partial surface plasmon-polariton localized at the metal-semiconductor interface penetration into air. In result the real part of the metal+air half-space effective dielectric function becomes closer (in absolute value) to the real part of the semiconductor dielectric function than in the case of a thick covering metal film. This leads to approaching the point of the surface plasmon-polariton resonance (where absolute values of these parts coincide) and, therefore, the enhancement of the surface plasmon-polariton excitation. The calculations were made for a particular example of InAs quantum dot layer embedded in GaAs matrix covered with an Au film. Its results indicate that for the 10 nm Au film the rate of this excitation becomes by 2.5 times, and for the 5 nm Au film - by 6-7 times larger than in the case of a thick (40 nm or more) Au film.

• 한국표면공학회지
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• 제48권1호
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• pp.11-22
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• 2015

Pd alloy hydrogen membranes for hydrogen purification and separation need thermal stability at high temperature for commercial applications. Intermetallic diffusion between the Pd alloy film and the porous metal support gives rise to serious problems in long-term stability of Pd alloy membranes. Ceramic barriers are widely used to prevent the intermetallic diffusion from the porous metal support. However, these layers result in poor adhesion at the interface between film and barrier because of the fundamentally poor chemical affinity and a large thermal stress. In this study, we developed Pd alloy membranes having a dense microstructure and saturated composition on modified metal supports by advanced DC magnetron sputtering and heat treatment for enhanced thermal stability. Experimental results showed that Pd-Cu and Pd-Ag alloy membranes had considerably enhanced long-term stability owing to stable, dense alloy film microstructure and saturated composition, effective diffusion barrier, and good adhesive interface layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.449-457
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• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.29-29
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• 1999

The synthesis of layered structures on the nanometer scale has become essential for continued improvements in the operation of various electronic and magnetic devices. Abrupt metal-metal interfaces are desired for applications ranging from metallization in semiconductor devices to fabrication of magnetoresistive tunnel junctions for read heads on magnetic disk drives. In particular, characterizing the interface structure between various transition metals (TM) and aluminum is desirable. We have used the techniques of MeV ion backscattering and channeling (HEIS), x-ray photoemission (ZPS), x-ray photoelectron diffraction(XPD), low-energy ion scattering (LEIS), and low-energy electron diffraction(LEED), together with computer simulations using embedded atom potentials, to study solid-solid interface structure for thin films of Ni, Fe, Co, Pd, Ti, and Ag on Al(001), Al(110) and Al(111) surfaces. Considerations of lattice matching, surface energies, or compound formation energies alone do not adequately predict our result, We find that those metals with metallic radii smaller than Al(e.g. Ni, Fe, Co, Pd) tend to form alloys at the TM-Al interface, while those atoms with larger atomic radii(e.g. Ti, Ag) form epitaxial overlayers. Thus we are led to consider models in which the strain energy associated with alloy formation becomes a kinetic barrier to alloying. Furthermore, we observe the formation of metastable fcc Ti up to a critical thickness of 5 monolayers on Al(001) and Al(110). For Ag films we observe arbitrarily thick epitaxial growth exceeding 30 monolayers with some Al alloying at the interface, possible driven by interface strain relief. Typical examples of these interface structures will be discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.242-242
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• 2010

산화 알루미늄($Al_2O_3$) 박막을 p-type Czochralski(CZ) Si 위에 Remote Plasma Atomic Layer Deposition(RPALD)을 이용하여 저온 공정으로 증착하였다. Photolithography 공정으로 grid 패턴을 형성한 후 열 증착기로 알루미늄을 증착하여 MIS-IL (Metal-Insulator-Semiconductor Inversion Layer) solar cell을 제작하였다. 반응소스로는 Trimethylaluminum (TMA)과 $O_2$를 이용하였다. $Al_2O_3$ 박막의 전기적 특성 평가를 위해 MIS capacitor를 제작하여 Capacitance-voltage (C-V), Current-voltage (I-V), Interface state density ($D_{it}$)를 평가하였으며 Solar simulator를 이용하여 MIS-IL Solar cell의 Efficiency을 측정하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• 한국재료학회지
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• 제27권7호
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• pp.364-368
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• 2017

We performed temperature dependent current-voltage (I-V) measurements to characterize the electrical properties of $Au/Al_2O_3/n-Ge$ metal-insulator-semiconductor (MIS) diodes prepared with and without $H_2O$ prepulse treatment by atomic layer deposition (ALD). By considering the thickness of the $Al_2O_3$ interlayer, the barrier height for the treated sample was found to be 0.61 eV, similar to those of Au/n-Ge Schottky diodes. The thermionic emission (TE) model with barrier inhomogeneity explained the final state of the treated sample well. Compared to the untreated sample, the treated sample was found to have improved diode characteristics for both forward and reverse bias conditions. These results were associated with the reduction of charge trapping and interface states near the $Ge/Al_2O_3$ interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.