• 한국정보통신학회논문지
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• 제26권5호
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• pp.682-687
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• 2022

터널링 전계효과 트랜지스터(tunneling field-effect transistor; TFET)로 적층된 3차원 적층형 집적회로(monolithic 3D integrated-circuit; M3DIC)에 대한 연구 결과를 소개한다. TFET는 MOSFET(metal-oxide-semiconductor field-effect transistor)와 달리 소스와 드레인이 비대칭 구조이므로 대칭구조인 MOSFET의 레이아웃과 다르게 설계된다. 비대칭 구조로 인해서 다양한 인버터 구조 및 레이아웃이 가능하고, 그 중에서 최소 금속선 레이어를 가지는 단순한 인버터 구조를 제안한다. 비대칭 구조의 TFET를 순차적으로 적층한 논리 게이트인 NAND 게이트, NOR 게이트 등의 M3DIC의 구조와 레이아웃을 제안된 인버터 구조를 바탕으로 제안한다. 소자와 회로 시뮬레이터를 이용해서 제안된 M3D 논리게이트의 전압전달특성 결과를 조사하고 각 논리 게이트의 동작을 검증한다. M3D 논리 게이트 별 셀 면적은 2차원 평면의 논리게이트에 비해서 약 50% 감소된다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

• Transactions on Electrical and Electronic Materials
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• 제16권5호
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• pp.254-259
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• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.867-872
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• 2016

We have investigated the channel mobility of AlGaN/GaN-on-Si recessed-metal-oxide-semiconductor-heterojunction field-effect transistors (recessed-MOS-HFET) with $SiO_2$ gate oxide. Both field-effect mobility and effective mobility for the recessed-MOS channel region were extracted as a function of the effective transverse electric field. The maximum field effect mobility was $380cm^2/V{\cdot}s$ near the threshold voltage. The effective channel mobility at the on-state bias condition was $115cm^2/V{\cdot}s$ at which the effective transverse electric field was 340 kV/cm. The influence of the recessed-MOS region on the overall channel mobility of AlGaN/GaN recessed-MOS-HFETs was also investigated.

• 전자통신동향분석
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• 제38권6호
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• 한국정보통신학회논문지
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• 제20권10호
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• pp.1927-1934
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• 2016

본 논문에서는 일반적인 실리콘 기반 n-MOSFET(n-type Metal Oxide Semiconductor Field Effect Transistor)의 절연 산화막 계면에서 방사선으로부터 유발되는 누설전류 경로를 차단하기 위하여 I형 게이트 n-MOSEFT 구조를 제안하였다. I형 게이트 n-MOSFET 구조는 상용 0.18um CMOS(Complementary Metal Oxide Semiconductor) 공정에서 레이아웃 변형 기법을 이용하여 설계되었으며, ELT(Enclosed Layout Transistor)와 DGA(Dummy Gate-Assisted) n-MOSFET와 같은 레이아웃 변형 기법을 사용한 기존 내방사선 전자소자의 구조적 단점을 개선하였다. 따라서, 기존 구조와 비교하여 반도체 칩 제작에서 회로 설계의 확장성을 확보할 수 있다. 또한, 내방사선 특성 검증을 위하여 TCAD 3D(Technology Computer Aided Design 3-dimension) tool을 사용하여 모델링과 모의실험을 수행하였고, 그 결과 I형 게이트 n-MOSFET 구조의 내방사선 특성을 확인하였다.

• 전기전자학회논문지
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• 제20권2호
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• pp.163-166
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• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• Transactions on Electrical and Electronic Materials
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• 제12권3호
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• pp.93-97
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• 2011

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 ${\mu}M$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 ${\mu}M$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($I_{SUB}$), drain to source leakage current ($I_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• 한국철도학회논문집
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• 제14권5호
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• pp.411-415
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• 2011

DC/DC컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 전력변환기이다. 전압모드 DC/DC 컨버터는 주기적으로 입력측에서 출력측으로 전달되는 에너지를 제어하는 기능을 수행하기 위해 MOSFET(산화물-반도체 전계 효과 트랜지스터), 인덕터, PWM 제어기(오실레이터, 연산증폭기, 비교기로 구성)를 이용한다. 본 논문에서 PWM(펄스폭 변조) 모듈과 스위칭모드로 제어하는 기본적인 승압과 강압컨버터를 연구하고, 전기적 특성을 SPICE로 시뮬레이션을 수행하며, 전력의 효율을 각 소자의 변화와 사양에 따라 분석하는데 있다.