• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1274-1276
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• 1993

The silicon-nitride films formed by laser CVD method are used for passivating GaAs surfaces. The electrical Properties of metal-insulator-GaAs structure are studied to determined the interfacial characteristics by C-V curves and deep level transient spectroscopy(DLTS). The SiN films are photolysisly deposited from $SiH_4\;and\;NH_3$ in the range of $100^{\circ}C-300^{\circ}C$ on P type, (100) GaAs. The hysteresis is reduced and interface trap density is lowered to $10^{12}-10^{13}$ at $100^{\circ}C-200^{\circ}C$. The surface leakage current is studied too. The passivated GaAs have a little leakage current compared to non passivated GaAs.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.1
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• pp.89-97
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• 2001

A microgyroscope, which vibrates in two orthogonal axes on the substrate plane, is designed and fabricated. The shuttle mass of the vibrating gyroscope consists of two parts. The one is outer shuttle mass which vibrates in driving mode guided by four folded springs attached to anchors. And the other is inner shuttle mass which vibrates in driving mode as the outer frame does and also can vibrate in sensing mode guided by four folded springs attached to the outer shuttle mass. Due to the directions of vibrating mode, it is possible to fabricate the gyroscope with simplified process by using polysilicon on insulator structure. Fabrication processes of the microgyroscope are composed of anisotropic silicon etching by RIE, gas-phase etching (GPE) of the buried sacrificial oxide layer, metal electrode formation. An eletromechanical model of the vibrating microgyroscope was modeled and bandwidth characteristics of the gyroscope operates at DC 4V and AC 0.1V in a vacuum chamber of 100mtorr. The detection circuit consists of a discrete sense amplifier and a noise canceling circuit. Using the evaluated electromechanical model, an operating condition for high performance of the gyroscope is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.268-268
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• 2016

Chemical sensors have attracted much attention due to their various applications such as agriculture product, cosmetic and pharmaceutical components and clinical control. A conventional chemical and biological sensor is consists of fluorescent dye, optical light sources, and photodetector to quantify the extent of concentration. Such complicated system leads to rising cost and slow response time. Until now, the most contemporary thin film transistors (TFTs) are used in the field of flat panel display technology for switching device. Some papers have reported that an interesting alternative to flat panel display technology is chemical sensor technology. Recent advances in chemical detection study for using TFTs, benefits from overwhelming progress made in organic thin film transistors (OTFTs) electronic, have been studied alternative to current optical detection system. However numerous problems still remain especially the long-term stability and lack of reliability. On the other hand, the utilization of metal oxide transistor technology in chemical sensors is substantially promising owing to many advantages such as outstanding electrical performance, flexible device, and transparency. The top-gate structure transistor indicated long-term atmosphere stability and reliability because insulator layer is deposited on the top of semiconductor layer, as an effective mechanical and chemical protection. We report on the fabrication of InGaZnO TFTs with silver nanowire as the top gate electrode for the aim of chemical materials detection by monitoring change of electrical properties. We demonstrated that the improved sensitivity characteristics are related to the employment of a unique combination of nano materials. The silver nanowire top-gate InGaZnO TFTs used in this study features the following advantages: i) high sensitivity, ii) long-term stability in atmosphere and buffer solution iii) no necessary additional electrode and iv) simple fabrication process by spray.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.107-112
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• 2020

Recently, the atomically thin transition-metal dichalcogenide (TMD) semiconductors have attracted much attention owing to their remarkable properties such as tunable bandgap with high carrier mobility, flexibility, transparency, etc. However, because these TMD materials have a significant drawback that they are easily degraded in an ambient environment, various attempts have been made to improve chemical stability. In this research article, I report a method to improve the air stability of WSe₂ one of the TMD materials via surface passivation with an h-BN insulator, and its application to field-effect transistors (FETs). With a modified hot pick-up transfer technique, a vertical heterostructure of h-BN/WSe₂ was successfully made, and then the structure was used to fabricate the top-gate bottom-contact FETs. The fabricated WSe₂-based FET exhibited not only excellent air stability, but also high hole mobility of 150 ㎠/Vs at room temperature, on/off current ratios up to 3×10⁶, and 192 mV/decade of subthreshold swing.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.463-469
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• 1996

The double insulating layer consisting of anodic oxide and ZnS was formed for HgCdTe metal insulator semiconductor(MIS) structure. ZnS was evaporated on the anodic oxide grown in H$_{2}$O$_{2}$ electrolyte. Recently, this insulating mechanism for HgCdTe MIS has been deeply studied for improving HgCdTe surface passivation. It was found through TEM observation that an interface layer is formed between ZnS and anodic oxide layers for the first time in the study of this area. EDS analysis of chemical compositions using by electron beam of 20.angs. in diameter and XPS depth composition profile indicated strongly that the new interface is composed of ZnO. Also TEM high resolution image showed that the structure of oxide layer has been changed from the amorphous state to the microsrystalline structure of 100.angs. in diameter after the evaporation of ZnS. The double insulating layer with the resistivity of 10$^{10}$ .ohm.cm was estimated to be proper insulating layer of HgCdTe MIS device. The optical reflectance of about 7% in the region of 5.mu.m showed anti-reflection effect of the insulating layer. The measured C-V curve showed the large shoft of flat band voltage due to the high density of fixed oxide charges about 1.2*10$^{12}$ /cm$^{2}$. The oxygen vacancies and possible cationic state of Zn in the anodic oxide layer are estimated to cause this high density of fixed oxide charges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.83-88
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• 2002

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1527-1533
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• 2000

Basically, a general characterization procedure based on the extraction of the characteristic impedance and propagation constant for analyzing a single MIS(Metal-Insulator-Semiconductor) transmission line is used. In this paper, an analysis for a new substrate shielding MIS structure consisting of grounded cross-bars at the interface between Si and SiO2 layer using the Finite-Difference Time-Domain (FDTD) method is presented. In order to reduce the substrate effects on the transmission line characteristics, a shielding structure consisting of grounded cross bar lines over time-domain signal has been examined. The extracted distributed frequency-dependent transmission line parameters and corresponding equivalent circuit parameters as well as quality factor have been examined as functions of cross-bar spacing and frequency. It is shown that the quality factor of the transmission line can be improved without significant change in the characteristic impedance and effectve dielectric constant.

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.