• Korean Journal of Materials Research
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• v.19 no.1
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• pp.28-32
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• 2009

Silicon carbide (SiC) is a promising material for power device applications due to its wide band gap (3.26 eV for 4H-SiC), high critical electric field and excellent thermal conductivity. The Schottky barrier diode is the representative high-power device that is currently available commercially. A field plate edge-terminated 4H-SiC was fabricated using a lift-off process for opening the Schottky contacts. In this case, Ni/Ti dual-metal contacts were unintentionally formed at the edge of the Schottky contacts and resulted in the degradation of the electrical properties of the diodes. The breakdown voltage and Schottky barrier height (SBH, ${\Phi}_B$) was 107 V and 0.67 eV, respectively. To form homogeneous single-metal Ni/4H-SiC Schottky contacts, a deposition and etching method was employed, and the electrical properties of the diodes were improved. The modified SBDs showed enhanced electrical properties, as witnessed by a breakdown voltage of 635 V, a Schottky barrier height of ${\Phi}_B$=1.48 eV, an ideality factor of n=1.04 (close to one), a forward voltage drop of $V_F$=1.6 V, a specific on resistance of $R_{on}=2.1m{\Omega}-cm^2$ and a power loss of $P_L=79.6Wcm^{-2}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.1-8
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• 2004

This paper describes the design of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been designed in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3 metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$ and the estimated power dissipation is less than 900 ㎽ with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.206.1-206.1
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• 2015

최근에 금속산화물을 증착하는 방법으로 용액공정이 주목 받고 있다. 용액 공정은 대기압에서 매우 간단한 방법으로 복잡한 공정과정을 요구하지 않기 때문에 박막을 경제적으로 간단하게 형성할 수 있다. 하지만 용액공정을 통해 형성한 박막에는 소자의 특성을 열화 시키는 solvent와 탄소계열의 불순물을 많이 포함하고 있어 고온의 열처리가 필수적이다. 박막의 품질을 향상시키기 위해서 다양한 열처리 방법들이 이용되고 있으며, 일반적인 열처리 방법으로는 furnace를 이용한 conventional thermal annealing (CTA)이 많이 이용되고 있다. 하지만, 최근에는 microwave를 이용한 공정이 주목 받고 있다. Microwave energy는 CTA보다 효과적으로 비교적 낮은 온도에서 높은 열처리 효과를 나타낸다. 본 실험은 n-type Silicon 기판에 solution-ZrO2 산화막을 형성 후, oven baking을 한 뒤, CTA와 microwave를 이용하여 solvent와 불순물을 제거 하였다. 전기적 특성을 확인하기 위해 solution ZrO2 산화막 위에 E-beam evaporator를 이용해 Ti 금속 전극을 증착하여 Metal-Oxide-Semiconductor (MOS) capacitor를 제작하였다. 다음으로, PRECISION SEMICONDUCTOR PARAMETER ANALYZER (4156B)를 이용하여, capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 비교하였다. 다음으로, CTA를 통하여 제작한 소자와 전기적 특성을 비교하였다. 그 결과, Microwave irradiation으로 열처리한 MOS capacitor 소자에서 capacitance 값과 flat band voltage, hysteresis 등이 개선되는 효과를 확인하였다. Microwave irradiation 열처리는 100oC 미만의 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 ZrO2 용액의 불순물과 solvent를 낮은 온도에서 제거하여 고품질 박막 형성에 매우 효과적이라는 것을 나타낸다. 따라서, microwave irradiation 열처리 방법은 비정질 산화막이 포함되는 박막 transistor 소자 제작에 대하여 결정적인 열처리 방법이 될 것으로 기대한다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.16.2-16.2
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• 2011

Graphene has attracted significant attention due to its unique characteristics and promising nanoelectronic device applications. For practical device applications, it is essential to synthesize high-quality and large-area graphene films. Graphene has been synthesized by eloborated mechanical exfoliation of highly oriented pyrolytic graphite, chemical reduction of exfoliated grahene oxide, thermal decomposition of silicon carbide, and chemical vapor deposition (CVD) on metal substrates such as Ni, Cu, Ru etc. The CVD has advantages over some of other methods in terms of mass production on large-areas substrates and it can be easily separated from the metal substrate and transferred to other desired substrates. Especially, plasma-enhanced CVD (PECVD) can be very efficient to synthesize high-quality graphene. Little information is available on the synthesis of graphene by PECVD even though PECVD has been demonstrated to be successful in synthesizing various carbon nanostructures such as carbon nanotubes and nanosheets. In this study, we synthesized graphene on $Ni/SiO_2/Si$ and Cu plate substrates with CH4 diluted in $Ar/H_2$ (10%) by using an inductively-coupled PECVD (ICPCVD). High-quality graphene was synthesized at as low as $700^{\circ}C$ with 600 W of plasma power while graphene layer was not formed without plasma. The growth rate of graphene was so fast that graphene films fully covered on substrate surface just for few seconds $CH_4$ gas supply. The transferred graphene films on glass substrates has a transmittance at 550 nm is higher 94%, indicating 1~3 monolayers of graphene were formed. FETs based on the grapheme films transferred to $Si/SiO_2$ substrates revealed a p-type. We will further discuss the synthesis of graphene and doped graphene by ICPVCD and their characteristics.

• Korean Journal of Materials Research
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• v.20 no.4
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• pp.217-222
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• 2010

Zirconium diboride (ZrB2) and mixed diboride of (Zr0.7Ta0.3)B2 containing 30 vol.% silicon carbide (SiC) composites were prepared by hot-pressing at $1800^{\circ}C$. XRD analysis identified the high crystalline metal diboride-SiC composites at $1800^{\circ}C$. The TaB2 addition to ZrB2-SiC showed a slight peak shift to a higher angle of 2-theta of ZrB2, which confirmed the presence of a homogeneous solid solution. Elastic modulus, hardness and fracture toughness were slightly increased by addition of TaB2. A volatility diagram was calculated to understand the oxidation behavior. Oxidation behavior was investigated at $1500^{\circ}C$ under ambient and low oxygen partial pressure (pO2~10-8 Pa). In an ambient environment, the TaB2 addition to the ZrB2-SiC improved the oxidation resistance over entire range of evaluated temperatures by formation of a less porous oxide layer beneath the surface SiO2. Exposure of metal boride-SiC at low pO2 resulted in active oxidation of SiC due to the high vapor pressure of SiO (g), and, as a result, it produced a porous surface layer. The depth variations of the oxidized layer were measured by SEM. In the ZrB2-SiC composite, the thickness of the reaction layer linearly increased as a function of time and showed active oxidation kinetics. The TaB2 addition to the ZrB2-SiC composite showed improved oxidation resistance with slight deviation from the linearity in depth variation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.6
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• pp.95-99
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• 2013

Furnace is currently the most important doping process using POCl3 in solar cell. However furnace need an expensive equipment cost and it has to purge a poisonous gas. Moreover, furnace typically difficult appling for selective emitters. In this study, we developed a new atmospheric pressure plasma source, in this procedure, we research the atmospheric pressure plasma doping that dopant is phosphoric acid($H_3PO_4$). Metal tube injected Ar gas was inputted 5 kV of a low frequency(scores of kHz) induced inverter, so plasma discharged at metal tube. We used the P type silicon wafer of solar cell. We regulated phosphoric acid($H_3PO_4$) concentration on 10% and plasma treatment time is 90 s, 150 s, we experiment that plasma current is 70 mA. We check the doping depth that 287 nm at 90 s and 621 nm at 150 s. We analysis and measurement the doping profile by using SIMS(Secondary Ion Mass Spectroscopy). We calculate and grasp the sheet resistance using conventional sheet resistance formula, so there are 240 Ohm/sq at 90 s and 212 Ohm/sq at 150 s. We analysis oxygen and nitrogen profile of concentration compared with furnace to check the doped defect of atmosphere.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.789-798
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• 1996

The double nitride layer Metal Nitride Oxide Semiconductor(MNOS) structures were fabricated by variating both gas ratio and nitride thickness, and by duplicating nitride deposited and one nitride layer MNOS structure to improve nonvolatile memory characteristics of MNOS structures by Low Pressure Chemical Vapor Deposition(LPCVD) method. The nonvolatile memory characteristics of write-in, erase, memory retention and degradation of Bias Temperature Stress(BTS) were investigated by the homemade automatic .DELTA. $V_{FB}$ measuring system. In the trap density double nitride layer structures were higher by 0.85*10$^{16}$ $m^{-2}$ than one nitride layer structure, and the AVFB with oxide field was linearly increased. However, one nitride layer structure was linearly increased and saturated above 9.07*10$^{8}$ V/m in oxide field. In the erase behavior, the hole injection from silicon instead of the trapped electron emission was observed, and also it was highly dependent upon the pulse amplitude and the pulse width. In the memory retentivity, double nitrite layer structures were superior to one nitride layer structure, and the decay rate of the trapped electron with increasing temperature was low. At increasing the number on BTS, the variance of AVFB of the double nitride layer structures was smaller than that of one nitride layer structure, and the trapped electron retention rate was high. In this paper, the double nitride layer structures were turned out to be useful in improving the nonvolatile memory characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.