• Journal of Institute of Convergence Technology
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• v.5 no.2
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• pp.21-25
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• 2015

This paper proposes a fabrication process of deposited layer with micro patterns that uses a combination of a pulsed laser beam machining and an electrodeposition. This process consists of the electrodeposition and the laser beam machining. The deposited layer on metal can be selectively eliminated by laser ablation. As a result, the deposited layer with micro patterns can be fabricated without a mask. The characteristics of the deposited layer on stainless steel were investigated according to the average power and marking speed in the pulsed laser beam machining. The optimal laser beam conditions for precise micro patterning of the deposited layer were determined. Finally, the deposited copper layer with micro text was successfully fabricated by the pulsed laser beam machining.

• Journal of the Korean Society for Precision Engineering
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• v.24 no.11
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• pp.108-115
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• 2007

We have designed a high transmission C-shaped aperture using finite differential time domain (FDTD) technique. The C-shaped aperture was fabricated in the aluminum thin film on a glass substrate using a focused ion beam (FIB) milling. Nano-size patterning was demonstrated with a vacuum contact device to keep tight contact between the Al mask and the photoresist. Using 405 nm laser, we recorded a 50 nm-size dot pattern on the photoresist with the aperture and analyzed the spot size dependent on the dose illuminated on the aperture.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.907-912
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• 2005

Micro-patterns of $Pb(Zr_{0.53}Ti_{0.47})O_3$, PZT, thin films with a MPB composition were deposited on $Pt/Ti/SiO_2/Si$ substrate from molecular-designed PZT precursor solution by using self-assembledmonolayer(SAM) as a template. This method includes deposition of SAM followed by the optical etching by exposing the SAM to the UV-light, leading to the patterned SAM as a selective deposition template. The pattern of SAM was formed by irradiating UV-light to the SAM on a substrate and/or patterned PZT thin film through a metal mask for the selective deposition of patterned PZT or lanthanum nickel oxide (LNO) precursor films from alkoxide-based precursor solutions. As a result, patterned ferroelectric PZT and PZT/LNO thin film capacitors with good electrical properties in micrometer size could be successfully deposited.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1921-1926
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• 2003

Nano-imprint technology has been vigorously studied by many researchers for it is one of the most promising technologies for manufacturing the pattern with its critical dimension below 100nm. In the nano-imprint technology, nano patterns are transferred on a polymer film and the transferred patterns are used as an etch mask to define the designed patterns on a substrate or a metal layer. To this end, it is important to keep the residual thickness of the imprinted polymer film uniform. In this study, a novel measurement technique to measure the residual thickness of films is proposed based on nanoindentation theory. This technique has advantages of saving time and measuring the residual thickness of highly-localized portions in comparison with other techniques, but has limitation of requiring calibration process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.881-886
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• 2003

This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1393-1398
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• 2009

We once have announced that we developed a horizontal large-area alignment system with an alignment accuracy of < ${\pm}3{\mu}m$ and an alignment time of < 30 seconds, a core process module for RGB direct pattering by using a fine metal mask, which can process a Gen 4 ($730{\times}920mm^2$) substrate for high resolution OLED products. In this article, we presents a brand-new vertical alignment system for a even larger substrate of Gen 5 and beyond which can provide a better alignment accuracy and a higher throughput. The newly developed system exhibits an alignment accuracy of < ${\pm}2{\mu}m$ and an alignment time of < 20 seconds which, we believe, can open a new era for manufacturing large-size OLED monitors and TVs.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.717-720
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• 2007

We fabricated the 3.5 inch QCIF AMOLED panel with ultra low temperature polycrystalline silicon TFT on the plastic substrate. To reduce the leakage current, we used the triple layered gate metal structure. To reduce the stress from inorganic dielectric layer, we applied the organic interlayer dielectric and the photoactive insulating layer. By using the interlayer dielectric as a capacitor, the mask steps are reduced up to five.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.173-179
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• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.