• 제목/요약/키워드: Metal guard ring

검색결과 13건 처리시간 0.027초

금속 가드 링이 SiC 쇼트키 다이오드의 항복전압에 미치는 영향 (Effect on Metal Guard Ring in Breakdown Characteristics of SiC Schottky Barrier Diode)

  • 김성진
    • 한국전기전자재료학회논문지
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    • 제18권10호
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    • pp.877-882
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    • 2005
  • In order to fabricate a high breakdown SiC-SBD (Schottky barrier diode), we investigate an effect on metal guard ring (MGR) in breakdown characteristics of the SiC-SBD. The breakdown characteristics of MGR-type SiC-SBD is significantly dependent on both the guard ring metal and the alloying time of guard ring metal. The breakdown characteristics of MGR-type SiC-SBDs are essentially improved as the alloying time of guard ring metal is increased. The SiC-SBD without MGR shows less than 200 V breakdown voltage, while the SiC-SBD with Al MGR shows approximately 700 V breakdown voltage. The improvement in breakdown characteristics is attributed to the field edge termination effect by the MGR, which is similar to an implanted guard ring-type SiC-SBD. There are two breakdown origins in the MGR-type SiC-SBD. One is due to a crystal defects, such as micropipes and stacking faults, in the Epi-layers and the SiC substrate, and occurs at a lower electric field. The other is due to the destruction of guard ring metal, which occurs at a higher electric field. The demolition of guard ring metal is due to the electric field concentration at an edge of Schottky contact metal.

플로팅 금속 가드링 구조를 이용한 Ga2O3 쇼트키 장벽 다이오드의 항복 특성 개선 연구 (Improved breakdown characteristics of Ga2O3 Schottky barrier diode using floating metal guard ring structure)

  • 최준행;차호영
    • 전기전자학회논문지
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    • 제23권1호
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    • pp.193-199
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    • 2019
  • 본 연구에서는 TCAD 시뮬레이션을 사용하여 산화갈륨 ($Ga_2O_3$) 기반 수직형 쇼트키 장벽 다이오드 고전압 스위칭 소자의 항복전압 특성을 개선하기 위한 가드링 구조를 이온 주입이 필요 없는 간단한 플로팅 금속 구조를 활용하여 제안하였다. 가드링 구조를 도입하여 양극 모서리에 집중되던 전계를 감소시켜 항복전압 성능 개선을 확인하였으며, 이때 금속 가드링의 폭과 간격 및 개수에 따른 항복전압 특성 분석을 전류-전압 특성과 내부 전계 및 포텐셜 분포를 함께 분석하여 최적화를 수행하였다. N형 전자 전송층의 도핑농도가 $5{\times}10^{16}cm^{-3}$이고 두께가 $5{\mu}m$인 구조에 대하여 $1.5{\mu}m$ 폭의 금속 가드링을 $0.2{\mu}m$로 5개 배치하였을 경우 항복전압 2000 V를 얻었으며 이는 가드링 없는 구조에서 얻은 940 V 대비 두 배 이상 향상된 결과이며 온저항 특성의 저하는 없는 것으로 확인되었다. 본 연구에서 활용한 플로팅 금속 가드링 구조는 추가적인 공정단계 없이 소자의 특성을 향상시킬 수 있는 매우 활용도가 높은 기술로 기대된다.

자기정렬된 Guard Ring을 갖는 새로운 쇼트키 다이오드 (A Novel Schottky Diode with the Self-Aligned Guard Ring)

  • 차승익;조영호;최연익
    • 대한전기학회논문지
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    • 제41권5호
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    • pp.573-576
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    • 1992
  • Novel A1-Si Schottky diodes with self-aligned guard rings have been proposed and fabricated using RIE(Reactive Ion Etch). The breakdown voltage of the Schottky diode with the guard ring has been drastically increased to 200V or more in comparison with 46V for the metal overlap Schottky diode.

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Guard Ring 구조에 따른 β-산화갈륨(β-Ga2O3) 전력 SBDs의 전기적 특성 비교 (Comparison of Electrical Properties of β-Gallium Oxide (β-Ga2O3) Power SBDs with Guard Ring Structures)

  • 이훈기;조규준;장우진;문재경
    • 한국전기전자재료학회논문지
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    • 제37권2호
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    • pp.208-214
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    • 2024
  • This reports the electrical properties of single-crystal β-gallium oxide (β-Ga2O3) vertical Schottky barrier diodes (SBDs) with a different guard ring structure. The vertical Schottky barrier diodes (V-SBDs) were fabricated with two types guard ring structures, one is with metal deposited on the Al2O3 passivation layer (film guard ring: FGR) and the other is with vias formed in the Al2O3 passivation layer to allow the metal to contact the Ga2O3 surface (metal guard ring: MGR). The forward current values of FGR and MGR V-SBD are 955 mA and 666 mA at 9 V, respectively, and the specific on-resistance (Ron,sp) is 5.9 mΩ·cm2 and 29 mΩ·cm2. The series resistance (Rs) in the nonlinear section extracted using Cheung's formula was 6 Ω, 4.8 Ω for FGR V-SBD, 10.7 Ω, 6.7 Ω for MGR V-SBD, respectively, and the breakdown voltage was 528 V for FGR V-SBD and 358 V for MGR V-SBD. Degradation of electrical characteristics of the MGR V-SBD can be attributed to the increased reverse leakage current caused by the guard ring structure, and it is expected that the electrical performance can be improved by preventing premature leakage current when an appropriate reverse voltage is applied to the guard ring area. On the other hand, FGR V-SBD shows overall better electrical properties than MGR V-SBD because Al2O3 was widely deposited on the Ga2O3 surface, which prevent leakage current on the Ga2O3 surface.

Characterization of small single photon avalanche diode fabricated using standard 180 nm CMOS process for digital SiPM

  • Jinseok Oh;Hakcheon Jeong;Min Sun Lee;Inyong Kwon
    • Nuclear Engineering and Technology
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    • 제56권8호
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    • pp.3076-3083
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    • 2024
  • In this work, single photon avalanche diodes (SPADs) were fabricated using the standard 180 nm complementary metal-oxide semiconductor process. Their small size of 15-16 µ m and low operating voltage made it possible to easily integrate them with readout circuits for compact on-chip sensors, particularly those used in the radiation sensor network of a nuclear plant. Four architectures were proposed for the SPADs, with a shallow trench isolation (STI) guard ring and different depletion regions designed to demonstrate the main performance parameters in each experimental configuration. The wide absorption region structure with PSD and a deep N-well could achieve a uniform electric field, resulting in a stable dark count rate (DCR). Additionally, the STI guard ring was implanted to mitigate the premature edge breakdown. A breakdown voltage was achieved for a low operating voltage of 10.75 V. The DCR results showed 286.3 Hz per ㎛2 at an excess voltage of 0.04 V. A photon detection probability of 21.48% was obtained at 405 nm.

Al-nSi 쇼트키 다이오드의 접합면 주위의 얇은 계단형 산화막 구조가 항복 전압에 미치는 영향 (The Effect of thin Stepped Oside Structure Along Contact Edge on the Breakdown Voltage of Al-nSi Schottky Diode)

  • 장지근;김봉렬
    • 대한전자공학회논문지
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    • 제20권3호
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    • pp.33-39
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    • 1983
  • 종래의 쇼트키 다이오드들이 가지는 금속중첩 및 P보호환 구조와 비교하여 금속-반도체 접합면 가장자리에 얇은 계단형 산화막(약1000Å) 구조를 갖는 새로운 소자들을 설계 제작하였다. 별은 계단형 산화막의 형성은 T.C.E. 산화공정으로 처리하였으며 이러한 새로운 소자들의 항복현상을 비교 검토하기 위하여 이들과 함께 동일한 소자 크기를 갖는 종래의 금속 중첩 쇼트키 다이오드와 P보호환 쇼트키 다이오드를 같은 폐이퍼상에 집적시켰고 항복전압에 대한 측정을 통해 고찰해 본 결과 금속-반도체 접합면 가장자리에 얇은 계단형 산화막 구조를 갖는 소자들은 종래의 쇼트키 다이오드들에 비해 항복현상에 있어서 월등한 개선을 보여 주는 것으로 나타났다.

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적색 중심 Optical Link용 Si pin Photodetector의 설계 및 제작 (Design and Fabrication of a Si pin Photodetector with Peak Spectral Response in the Red Light for Optical Link)

  • 장지근;김윤희;이지현;강현구;이상열
    • 마이크로전자및패키징학회지
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    • 제8권1호
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    • pp.1-4
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    • 2001
  • 새로운 구조의 APF optical link용 Si pin photodetector를 제작하고 그 특성을 분석하였다. 제작된 소자는 금속-반도체 접촉주위에 $p^{+}$-guard ring구조와 광이 입사되는 수광면에 그물망 모양의 얕은 $p^{+}$-확산영역을 갖는다. 제작된 소자의 전기.광학적 특성을 -5 V의 동작전압에서 측정한 결과, 접합 커패시턴스와 암전류는 각각 4 pF와 180 pA로 나타났으며 광신호 전류와 감도특성는 670 nm이 중심파장을 갖는 2.2 $\mu$W의 입사광 전력 아래에서 각각 1.22 $\mu$A와 0.55 A/W로 나타났다. 제작된 소자는 650~700 nm의 파장영역에서 최대 spectral response를 보이고 있으며 낮은 점한 커패시턴스와 우수한 신호분리능력으로 인해 red light optics응용에서 광신호 검출에 적합하게 사용될 수 있을 것으로 기대된다.

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CMOS공정에 의한 SSIMT의 제작 및 특성 (Fabrication and characteristics of SSIMT using a CMOS Process)

  • 송윤귀;임재환;정귀상;김남호;류지구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.168-171
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    • 2002
  • A SSIMT(Suppressed Sidewall Injection Magnetotransistor) sensor with high linearity is presented in this thesis. The prototype is fabricated by using the Hynix 0.6$\mu\textrm{m}$ P-substrate twin-well double poly three-metal CMOS Process. The fabricated SSIMT shows that variation of the collector current is extremely linear by varing the magnetic induction from -200mT to 200mT at I$\_$B/=500${\mu}$A, V$\_$CE/=2V and V$\_$SUB/=5V. The relative sensitivity is up to 120%/T. At B = 0, magnetic offset is about 79mT, there relative sensitivity is 30.5%/T. The nonlinearity of the fabricated SSIMT is measured about 1.4%.

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Spiral 인덕터 간 격리방법에 따른 Electromagnetic 커플링 효과 (EM Coupling Effect of sprint inductors by isolation methode in standard CMOS process)

  • 최문호;김한석;정성일;김영석
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.91-92
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    • 2005
  • The electromagnetic coupling effect in standard CMOS process is simulated and evaluated. EM coupling transfer characteristic between planar spiral inductors by isolation methode in standard CMOS have simulated and measured. Measurement results show that suppression of EM coupling effect by ground guardring. The evaluated structures are fabricated 1P5M(one poly, five metal) 0.25um standard CMOS process. These measurement results provide a isolation design guidelines in standard CMOS process for Rf coupling suppression.

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RFID tag 집적화를 위한 $0.18{\mu}m$ 표준 CMOS 공정을 이용한 쇼트키 다이오드의 제작 (Fabrication of Schottky diodes for RFID tag integration using Standard $0.18{\mu}m$ CMOS process)

  • 심동식;민영훈
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.591-592
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    • 2006
  • Schottky diodes for Radio-frequency identification (RFID) tag integration on chip were designed and fabricated using Samsung electronics System LSI standard $0.18{\mu}m$ CMOS process. Schottky diodes were designed as interdigitated fingers array by CMOS layout design rule. 64 types of Schottky diode were designed and fabricated with the variation of finger width, length and numbers with a $0.6{\mu}m$ guard ring enclosing n-well. Titanium was used as Schottky contact metal to lower the Schottky barrier height. Barrier height of the fabricated Schottky diode was 0.57eV. DC current - voltage measurements showed that the fabricated Schottky diode had a good rectifying properties with a breakdown voltage of -9.15 V and a threshold voltage of 0.25 V.

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