• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.373-373
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• 2014

Resistive-change random access memory (ReRAM) device is one of the promising candidates owing to its simple structure, high scalability potential and low power operation. Many resistive switching devices using transition metal oxides materials such as NiO, Al2O3, ZnO, HfO2, $TiO_2$, have attracting increased attention in recent years as the next-generation nonvolatile memory. Among various transition metal oxides materials, HfO2 has been adopted as the gate dielectric in advanced Si devices. For this reason, it is advantageous to develop an HfO2-based ReRAM devices to leverage its compatibility with Si. However, the annealing temperature of these high-k thin films for a suitable resistive memory switching is high, so there are several reports for low temperature process including microwave irradiation. In this paper, we demonstrate the bipolar resistive switching characteristics in the microwave irradiation annealing processed Ag/HfO2/Pt ReRAM device. Compared to the as-deposited Ag/HfO2/Pt device, highly improved uniformity of resistance values and operating voltage were obtained from the micro wave annealing processed HfO2 ReRAM device. In addition, a stable DC endurance (>100 cycles) and a high data retention (>104 sec) were achieved.

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.182-187
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• 2011

In this paper, PBTI characteristics of NMOSFETs with La incorporated HfSiON and HfON are compared in detail. The charge trapping model shows that threshold voltage shift (${\Delta}V_{\mathrm{T}}$) of NMOSFETs with HfLaON is greater than that of HfLaSiON. PBTI lifetime of HfLaSiON is also greater than that of HfLaON by about 2~3 orders of magnitude. Therefore, high charge trapping rate of HfLaON can be explained by higher trap density than HfLaSiON. The different de-trapping behavior under recovery stress can be explained by the stable energy for U-trap model, which is related to trap energy level at zero electric field in high-k dielectric. The trap energy level of two devices at zero electric field, which is extracted using Frenkel-poole emission model, is 1,658 eV for HfLaSiON and 1,730 eV for HfLaON, respectively. Moreover, the optical phonon energy of HfLaON extracted from the thermally activated gate current is greater than that of HfLaSiON.

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• 대한금속재료학회지
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• 제48권3호
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• 한국진공학회지
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• 제17권5호
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• pp.461-465
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• 2008

적층 박막 내에서의 상변화는 주변 층에 영향을 준다. 결정화가 게이트 절연층에 주는 영향이 제거된 선결정화법(precrystallization)이 금속 유도 일측면 결정화(metal-induced unilateral crystallization)에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성에 미치는 영향에 대하여 연구하였다. 이 방법으로 만들어진 소자는 일반적인 후 결정화(postcrystallization) 소자에 비하여 높은 전류 구동력을 보였다. 여기에 본 연구는 DC bias에 의한 ring oscillator의 특성 변화를 연구하였다. 선결정화된 실리콘 박막을 이용하여 제작한 PMOS inverter는 후결정화된 실리콘 박막을 이용하여 제작한 inverter에 비하여 매우 동적(dynamic)이고도 안정적인 특성을 보였다.

• Design & Manufacturing
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• 제11권3호
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• pp.29-34
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• 2017

Increased demand for parts with micro-pattern structure made of metals, ceramics, and composites in various fields such as medical ultrasonic sensors, CT collimators, and ultra-small actuator parts. Micro powder injection molding (PIM) is a technology for manufacturing micro size, high volume, complex, precision, net-shape components from either metal or ceramic powder. In the present study, a standard mold with a variable insert core capable of producing various micro patterns was investigated. An injection molding test was performed on a standard mold using a line type micro-pattern core having an aspect ratio of 2, a slenderness ratio of 70, a pattern size of $200{\mu}m$, and a pattern spacing of $150{\mu}m$. During the filling process, the deformation of the mold with large aspect ratio and slenderness ratio was analyzed by the experiment and the numerical simulation according to the position of the gate. We proposed a mold structure that minimizes mold deformation by gate modification and enables uniform pattern filling behavior.

• 한국주조공학회지
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• 제32권2호
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• pp.65-74
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• 2012

In this paper, we present the results of our studies on optimal die design towards development of a vacuum die casting process to fabricate fuel cell bipolar plate with micro-channel array. Cavity and overflow shape is designed by computational filling analysis of MAGMA soft. Optimal die design consists of seven overflows at the end of cavity and three overflows at each side wall of cavity. The molten metal that passed the gate and reached the side wall flowed into the side overflow, no turbulent flow occurred, and the filling behavior and velocity distribution were uniform. In addition, partially solidified molten metal passing through the channel was perfectly eliminated by overflow without back-flow. When vacuum pressure, injection speed of low and high region was 300 mbar, 0.3 m/s and 2.5 m/s respectively with Silafont 36 die casting alloy, sound sample without casting defects was obtained. The experimental results are nearly consistent with simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.239-244
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• 1998

Piezoelectric pressure sensors and pyroelectric infrared detectors based on ZnO thin film have been integrated with GaAs metal-semiconductor field effect transistor (MESFET) amplifiers. Surface micromachining techniques have been applied in a GaAs MESFET process to form both microsensors and electronic circuits. The on-chip integration of microsensors such as pressure sensors and infrared detectors with GaAs integrated circuits is attractive because of the higher operating temperature up to 200 oC for GaAs devices compared to 125 oC for silicon devices and radiation hardness for infrared imaging applications. The microsensors incorporate a 1${\mu}$m-thick sputtered ZnO capacitor supported by a 2${\mu}$m-thick aluminum membrane formed on a semi-insulating GaAs substrate. The piezoelectric pressure sensor of an area 80${\times}$80 ${\mu}$m2 designed for use as a miniature microphone exhibits 2.99${\mu}$V/${\mu}$ bar sensitivity at 400Hz. The voltage responsivity and the detectivity of a single infrared detector of an area 80${\times}$80 $\mu\textrm{m}$2 is 700 V/W and 6${\times}$108cm$.$ Hz/W at 10Hz respectively, and the time constant of the sensor with the amplifying circuit is 53 ms. Circuits using 4${\mu}$m-gate GaAs MESFETs are fabricated in planar, direct ion-implanted process. The measured transconductance of a 4${\mu}$m-gate GaAs MESFET is 25.6 mS/mm and 12.4 mS/mm at 27 oC and 200oC, respectively. A differential amplifier whose voltage gain in 33.7 dB using 4${\mu}$m gate GaAs MESFETs is fabricated for high selectivity to the physical variable being sensed.

• Transactions on Electrical and Electronic Materials
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• 제14권1호
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• pp.32-35
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• 2013

In this paper, a manufacturing process was developed for fabricating high-quality AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide (SiC) substrates. Various conditions and processing methods regarding the ohmic contact and pre-metal-deposition $BCl_3$ etching processes were evaluated in terms of the device performance. In order to obtain a good ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallization scheme under different rapid thermal annealing (RTA) temperature and time. A $BCl_3$-based reactive-ion etching (RIE) method was performed before the ohmic metallization, since this approach was shown to produce a better ohmic contact compared to the as-fabricated HEMTs. A HEMT with a 0.5 ${\mu}m$ gate length was fabricated using this novel manufacturing process, which exhibits a maximum drain current density of 720 mA/mm and a peak transconductance of 235 mS/mm. The X-band output power density was 6.4 W/mm with a 53% power added efficiency (PAE).