• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.6
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• pp.242-245
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• 2005

We compared and analyzed ASER (Accelerated Soft Error Rate) for cell structures and metal plate capacitance in the fabricated 16M SRAM. Application of the BNW (Buried NWELL) lowered the ASER value compared to the normal well structure. By applying the metal plate capacitor with the BNW, the lowest ASER value can be obtained. The thinner oxide thickness of the metal plate capacitor provides higher capacitance and lower ASER value. The ASER is improved from 2200 FIT to 1000 FIT after sole application of the BNW. However, it is dramatically improved to 15 FIT once the metal plate capacitor is additionally applied.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.302-307
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• 1988

A noble interconnection line capacitance measurement method to be able to remove the measurement errors from the probe pad to substrate stray capacitance has been proposed and verified. The measurement errors in the capacitance measurement, which usually be involved from the probe pad to substrate stray capacitance, can easily be removed by isolating the metal probe pad from the substrate with a grounded shield plate between the probe pad the substrate. The measurement results by using this improved capacitance measurement method were compared with the calculations by two-dimensional computer simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.55-57
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• 2005

In this study, modeling of the CD stud welding system was conducted considering mechanical and electrical components. The electrical components such as arc resistance, cable resistance, capacitance, internal resistance and cable inductance were found to affect the output waveform significantly. The calculated results showed food agreements with the experiment results within 20% error. The main defect of CD stud welding with 1010 steel stud and SS400 steel plate was the void trapped between stud and base metal. The effect of the spring force and stud tip size on void formation was investigated.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1615-1620
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• 2010

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

• Journal of the Korean Magnetics Society
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• v.4 no.2
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• pp.168-172
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• 1994

This paper reports a method measuring magnetostriction, Young's moduli of a substrate and film and ${\Delta}\;E$-effect with one apparatus. A substrate deposited with a thin magnetic film is parallely cantilevered paraIled to a metal plate electrode, forming a capacitive cell. The cantilever deflects due to own weight, applied electric and magnetic filed. The smaIl change of the capacitance caused by this deflection is measured by a sensitive capaci-tance bridge. Young's modulus, magnetostriction and ${\Delta}\;E$ effect can be calculated by theoretical analysis with the weight, applied field and deflection data.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.713-718
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• 2006

We designed and fabricated, in this paper, a quintuple band folded monopole antenna for the mobile phone handset that can be provided multiple mobile services. Antenna design was based on the compensation of series antenna capacitance with the expansion of physical antenna length by the proper folding structure. It's shown that this antenna satisfies quintuple service band as CDMA/GSM/DCS/USPCS/WCDMA, and is more cost competitive than conventional metal plate pressing method by applying on flexible PCB technology. Measured maximum gain on quintuple band were $-2.51{\sim}+1.82 dBi$, and radiation patterns were also shown nearly omnidirectional on all bands.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.80-85
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• 2015

In this paper, we present, an indstrial RFID layered microstrip patch antenna is designed using an inset feed method in order to improve recognition rates in a long distance as tags are attached to metal object by improving a problem of feeding power in fabricating metal tags and reducing effects of metallic object. The inset feed shows a distinctive characteristic that has no separation between emitters and feed lines differing from a structure with the conventional inductive coupling feed. This structure makes possible to produce a type that presents a low antenna height and enables impedance coupling for tag chips. Although it shows a difficulty in the impedance coupling due to increases in the parasite capacitance between a ground plane and an emitter in an antenna according to decreases in the height of a tag antenna, it may become a merit in designing the tag antenna because the antenna impedance can be determined as an inductive manner if a shorted structure is used for feeding power. Therefore, in this paper the microstrip patch antenna is designed as a modified type and applies the inset feed in order to reduce effects of metallic objects where the antenna is be attached. Also, the antenna uses a multi-layer structure that includes a metal plate between radiator and ground instead of using a single layer.