• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.56-56
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• 2008

ZnO Oxide TFT with organic dielectric was prepared. ZnO thin film as active channel was prepared by plasma enhanced atomic deposition technique. Organic dielectric was spin coated on the gate metal. The structure of prepared TFT is bottom gate type and top contact structure. The characterization of oxide TFT was performed. We obtained the mobility of $0.7cm^2$/Vs, the threshold voltage of -14V, and the on-off ratio of $10^4$. We also obtained good output characterization with solid saturation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.2
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• pp.87-91
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• 2013

Carbon-nanotube field-effect transistors (CNFETs) have drawn wide attention as one of the potential substitutes for metal-oxide-semiconductor field-effect transistors (MOSFETs) in the sub-10-nm era. Output characteristics of coaxially gated CNFETs were simulated using FETToy simulator to reveal the dependence of drain current on the nanotube diameter and gate oxide thickness. Nanotube diameter and gate oxide thickness employed in the simulation were 1.5, 3, and 6 nm. Simulation results show that drain current becomes large as the diameter of nanotube increases or insulator thickness decreases, and nanotube diameter affects the drain current more than the insulator thickness. An equation relating drain saturation current with nanotube diameter and insulator thickness is also proposed.

• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.867-872
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• 2016

We have investigated the channel mobility of AlGaN/GaN-on-Si recessed-metal-oxide-semiconductor-heterojunction field-effect transistors (recessed-MOS-HFET) with $SiO_2$ gate oxide. Both field-effect mobility and effective mobility for the recessed-MOS channel region were extracted as a function of the effective transverse electric field. The maximum field effect mobility was $380cm^2/V{\cdot}s$ near the threshold voltage. The effective channel mobility at the on-state bias condition was $115cm^2/V{\cdot}s$ at which the effective transverse electric field was 340 kV/cm. The influence of the recessed-MOS region on the overall channel mobility of AlGaN/GaN recessed-MOS-HFETs was also investigated.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.108-109
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• 2014

본 논문에서는 gate와 drain bias stress하에서의 a-IGZO thin-film transistors (TFTs)의 비대칭 열화 메커니즘 분석을 진행하였다. Gate와 drain bias stress하에서의 a-IGZO TFT의 열화 현상은 conduction band edge 근처에 존재하는 oxygen vacancy-related donor-like trap의 발생으로 예상되며, TFT의 channel layer 내에서의 비대칭 열화현상은 source의 metal과 a-IGZO layer간의 contact에 전압이 인가되었을 경우, reverse-biased Schottky diode에 의한 source 쪽에서의 높은 electric field가 trap generation을 가속화시킴으로써 일어나는 것임을 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.551-552
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• 2006

Plasma-induced charging damage was been measured during TaN gate electrode of MISFET(TaN/$HfO_2$/Si) or interconnection metal etching step using large antenna structures. The results of these experiments were obtained that $HfO_2$ gate dielectric layer was affected about plasma charging effects and damage increased with F-N tunneling. Therefore, the etching conditions should be optimized to avoid the defects caused by plasma charging.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1044-1046
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• 2009

Here we report the architecture for a non-volatile n-type memory paper field-effect transistor. The device is built using the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in an ionic resin), which act simultaneously as substrate and gate dielectric, with amorphous GIZO and IZO oxides as gate and channel layers, respectively. This is complemented by the use of continuous patterned metal layers as source/drain electrodes.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1193-1196
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• 2009

Low resistivity interconnection and high-mobility channel are required to realize ultrahigh-definition LCDs such as 4k ${\times}$ 2k TVs. We evaluated fully Cu-based gate and Source/Drain interconnections, consisting of stacked pure-Cu/Cu-Mn layers for TFT-LCDs, and found the underlying Cu-Mn alloy film has superior adhesion to glass substrates and CVD-SiOx films. It was also confirmed that wet etching of the Cu/Cu-Mn films without residues and low contact resistance with both channel IGZO and pixel ITO films can be obtained. It is thus considered that the stacked Cu/Cu-Mn structure is one of candidates to replacing conventionally pure-Cu/refractory metal.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.958-961
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• 2007

The electrical characteristics of organic thin-filmtransistor (OTFTs) can be improved by inserting adhesion layer on gate dielectrics. Adhesion layer was used as polymeric adhesion layer deposited on inorganic gate insulators such as silicon dioxide $(SiO_2)$ and it was formed by vapor deposition polymerization (VDP) instead of spin-coating process. The OTFTs obtained the on/off ratio $of{\sim}10^4$, threshold voltage of 1.8V, subthreshold slop of 2.9 V/decade and field effect mobility about $0.01\;cm^2/Vs$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.4
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• pp.361-366
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• 2004

The interface stability of Ta-Mo alloy film on SiO$_2$ was investigated. Ta-Mo alloy films were formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power, When the atomic composition of Ta was about 91％, the measured work function was 4.24 eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy film and SiO$_2$, C-V and XRD measurements were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and 90$0^{\circ}C$. Even after 90$0^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.