• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.104-109
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• 2008

A simple and efficient way of modeling backgating in GaAs MESFET's is presented through depletion width modulation of Schottky junction and channel-substrate interface. It is shown semi-empirically that such a modulation of depletion widths causes serious troubles in designing precision circuits since backgating drastically reduces threshold voltage of MESFET as well as drain current. Finally, some of the results are compared with reported experimental results. This model may serve as a starting point for rigorous characterization of backgating effect on various device parameters of GaAs MESFET's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.185-192
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• 1995

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.210-224
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• 2006

A new analytical model for the static I-V characteristics of GaAs MESFET’s under optically controlled conditions in both linear and saturation region is presented in this paper. The novelty of the model lies in characterizing both photovoltaic (external, internal) and photoconductive effects. Deep level traps in the semi insulating GaAs substrate are also included in this model. Finally, effect of backgate voltage on I-V characteristics is explained analytically for the first time in literature. Small signal parameters of GaAs MESFET are derived under both dark and illuminated conditions. Some of the results are compared with reported experimental results to show the validity of the proposed model. Since accurate dc modeling is the key to accurate ac modeling, this model is very useful in the designing of photonic MMIC’s and OEIC’s using GaAs MESFET.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.28-35
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• 1993

The MESFET can be used as a three-terminal varactor by employing gate depletion capacitance Cg. In this paper, a novel VCDRO(voltage controlled dielecric resonator oscillator) is designed to apply VCDRO with this concept. The VCDRO produced 6.33dBm output power at a frequency of 11.058GHz and tunning bandwidth of 45MHz. The advantage of using the MESFET as a three-terminal varactor is to let the MESFET play both roles at the same time, thus simplifying the circuit configuration and fabrication. This finding demonstrates the potential of using both real and imaginary parts of the equivalent impedance of the active device.

• ETRI Journal
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• v.13 no.4
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• pp.35-41
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• 1991

저전력 고집적 GaAs 디지틀 IC에 적합한 기본 논리회로인 DCFL (Direct Coupled FET Logic) 을 구현하기 위한 소자로 WSi게이트 MESFET 공정을 연구하였으며, 이와 함께 TiPtAu 게이트 소자를 제작하였다. MESFET 의 제작은 내열성게이트를 이용한 자기정렬 이온주입 공정을 사용하였으며 주입된 Si 이온은 급속열처리 방법으로 활성화하였다. 또한 제작공정중 저항성 접촉의 형성은 절연막을 이용한 리프트 - 오프 공정을 이용하였다. 제작된 WSi게이트 MESFET은 $1\mum$ 게이트인 경우 222mS/mm의 트랜스컨덕턴스를 나타내어 우수한 동작특성과 집적회로 공정의 적합성을 보였으며 이와 동등한 공정조건으로 제작된 TiPtAu 게이트 MESFET 은 2" 기판 내에서 84mV의 임계전압 변화를 나타내었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.445-448
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• 1999

In this Paper, we present simple physical model of the Capacitance characteristics for GaAs MESFET\`s in wide temperatures. In this model, gate-source and gate-drain capacitances are represented by analytical expressions which are classified into three different regions for bias voltage. This model contained the temperature dependent variable that is the built-in voltage and the depletion width. Using the equations obtained in this work a submicron gate length MESFET has simulated and theoretical result are in good agreement with the experimental measurement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.82-85
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• 2000

The less sensitive structure to the surface effect has been presented utiliting an undoped GaAs layer on the n-GaAs channel. The undoped layer has been found to be effective to supress the frequency dispersion phenomena caused by a surface trapping effect and to raise the MESFET's performance. The gate structure, with an undoped layer underneath the gate metal has been found to be effective to improve the breakdown voltage. GaAs MESFETS with different physical structures are fabricated and DC characteristics are measued. GaAs MESFET's are fabricated on epi-wafers which have an undoped GaAs layer in between n+ and n GaAs layers grown by MBE.

• ETRI Journal
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• v.13 no.4
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• pp.10-24
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• 1991

본 연구에서는 기상 성장법 (VPE : vapor phase epitaxy) 으로 성장된 $n^+(Si:2X10^18cm^-3)$/$n(Si:1x10^17cm^-3)$구조의 시편 위에 SiN 과 감광막 등 식각 선택비가 서로 다른 두 물질로 보호된 소스와 드레인 사이의 게이트 형성 영역을 건식식각과 습식식각방법으로 리세스 에칭을 하여 형성한 후, 게이트를 자기정렬하여 형성시킬 수 있는 이중 리세스공정 기술을 개발하였고, 이를 통하여 전력용 MESFET 소자를 제작하였다.게이트 형성부분의 wide recess 폭은 건식식각으로 SiN을 측면식각(lateral etch) 함으로써 조절하였는데, 이 방법을 사용하여 MESFET 소자의 임계전압을 조절할 수 있고, 동시에 소스-드레인 항복전압을 30V 까지 향상시킬 수 있었다. 소스-드레인 항복전압은 wide recess 폭이 증가함에 따라, 그리고 게이트 길이가 길어짐에 따라 증가하는 경향을 보여주었다. 이 방법으로 제작한 여러종류의 MESFET 중에서 게이트 길이가 $2\mum$이고 소스-게이트 간격이 $3 \mum$인 MESFET의 전기적 특성은 최대 트랜스컨덕턴스가 120 mS/mm, 게이트 전압이 0.8V 일 때 포화드레인전류가 170~190mA/mm로 나타났다. 제작된 MESFET이 ($NH_4$)$_2$$S_x$ 용액에 담금처리될때 , 공기중에 노출된 게이트-드레인 사이의 n-GaAs층의 표면이 유황으로 보호되어 공기노출에 의한 표면 재산화막의 형성이 억제되었기 때문으로 사료된다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.11a
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• pp.94-94
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• 1999

• Proceedings of the Materials Research Society of Korea Conference
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• 1999.05a
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• pp.110-110
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• 1999