• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.47-52
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• 2002

A processing method is developed for preparing sol-gel derived $Pb(Zr_{1-x}Ti_x)O_3$ (x=0.5) thin films on Pt-Ir($Pt_{80}Ir_{20}$)-alloy substrates. The as-deposited layer was dried on a plate in air at $70^{\circ}C$. And then it was baked at $1500^{\circ}C$, annealed at $450^{\circ}C$ and finally annealed for crystallization at various temperatures ranging from $580^{\circ}C$ to $700^{\circ}C$ for 1hour in a tube furnace. The thickness of the annealed film with three layers was $0.3{\mu}m$. Crystalline properties and surface morphology were examined using X-ray diffractometer (XRD). Electrical properties of the films such as dielectric constant, C-V, leakage current density were measured under different annealing temperature. The PZT thin film which was crystallized at $600^{\circ}C$ for 60minutes showed the best structural and electrical dielectric constant is 577. C-V measurement show that $700^{\circ}C$ sample has window memory volt of 2.5V and good capacitance for bias volts. Leakage current density of every sample show $10^{-8}A/cm^2$ r below and breakdown voltage(Vb) is that 25volts.

• 한국재료학회지
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• 제10권4호
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• pp.270-275
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• 2000

Metal/ferroelectric/insulator/semiconductor(MFIS)-Field Effect Transistor을 위한 Pt/YMnO$_3$/Y$_2$O$_3$/Si 구조를 제조하여 MFIS 구조의 특성에 미치는 $Y_2$O$_3$박막의 영향을 고찰하였다. PLD법을 이용하여 p=type Si(111) 기판 위에 증착시킨 $Y_2$O$_3$박막은 증착온도와 관계없이 (111)방향으로의 우선배향성을 갖고 결정화 되었다. 실리콘 위에 바로 MOCVD법에 의해 강유전체 YMnO$_3$박막을 증착시킨 경우 실리콘과의 계면에서 Mn이 부족한 층이 형성되지만 $Y_2$O$_3$가 실리콘과 YMnO$_3$사이에 삽입된 경우는 $Y_2$O$_3$바로 위에서부터 화학양론비에 일치하는 양질의 YMnO$_3$박막을 얻을 수 있었다. 85$0^{\circ}C$, 100mtorr의 진공분위기에서 열처리한 YMnO$_3$박막은 $Y_2$O$_3$가 삽입된 경우 memory window 값이 $Y_2$O$_3$가 삽입되지 않은 경우보다 더 큰 값을 보였으며 5V에서 1.3V의 값을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.73-74
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• 2006

Ferroelectric thin films have been widely investigated for future nonvolatile memory application. We fabricated the BLT ($(Bi,La)_4Ti_3O_{12}$) films on Si using a STA ($SrTa_2O_6$) buffer layer BLT and STA film were prepared by sol-gel method. Measurement data by XRD and AFM, showed that BLT film and STA films were well crystallized and a good surface morphology. From C-V measurement reward that the Au/BLT/STA/Si structure showed a clockwise hysteresis loop with a memory window of 1.5 V for the bias voltage sweep of ${\pm}5$ V. From results, the Au/BLT/STA/Si structure is useful for FeFETs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.75-78
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• 1998

The SONOSFET Shows low operation voltage, high cell density, anti good endurance due to modified Fowler-Nordheim tunneling as memory charge injection method. In this paper, therefore, the NOR-type Flash EEPROM composed of SONOSFET, which has fast lead operation speed and Random Access characteristics, is proposed. An 8${\times}$8 bit NOR-type SONOSFET Flash EEPROM had been designed and its electrical characteristics were verified. Read/Write/Erase operations of it were verified with the spice parameters of SONOSFETs which had Oxide-Nitride-Oxide thickness of 65${\AA}$-165${\AA}$-35${\AA}$ and that of scaled down as 33${\AA}$-53${\AA}$-22${\AA}$, respectively. When the memory window of the scaled-down SONOSFET with 8V operation was similar to that of the SONOSFET with 13V operation, the Read operation delay times of the scaled-down SONOSFET were 25.4ns at erase state and 32.6ns at program state, respectively, and those of the SONOSFET were 23.5ns at erase state and 28.2ns at program state, respectively.

• 한국전기전자재료학회논문지
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• 제29권3호
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• pp.135-140
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• 2016

In this study, we developed the solution-processed PMMA-$HfO_x$ hybrid ReRAM devices to overcome the respective drawbacks of organic and inorganic materials. The performances of PMMA-$HfO_x$ hybrid ReRAM were compared to those of PMMA- and $HfO_x$-based ReRAMs. Bipolar resistive switching behavior was observed from these ReRAMs. The PMMA-$HfO_x$ hybrid ReRAMs showed a larger operation voltage margin and memory window than PMMA-based and $HfO_x$-based ReRAMs. The reliability and electrical instability of ReRAMs were remarkably improved by blending the $HfO_x$ into PMMA. An Ohmic conduction path was commonly generated in the LRS (low resistance state). In HRS (high resistance state), the PMMA-based ReRAM showed SCLC (space charge limited conduction). the PMMA-$HfO_x$ hybrid ReRAM and $HfO_x$-based ReRAM revealed the Pool-Frenkel conduction. As a result of flexibility test, serious defects were generated in $HfO_x$ film deposited on PI (polyimide) substrate. On the other hand, the PMMA and PMMA-$HfO_x$ films showed an excellent flexibility without defect generation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• Journal of Korean Vacuum Science & Technology
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• 제4권1호
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• pp.6-10
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• 2000

Ferroelectric YMnO$_3$ thin films were deposited on $Y_2$O$_3$/si(100) substrates by metalorganic chemical vapor deposition. The YMnO$_3$ thin films annealed in vacuum ambient (100 mTorr) above 75$0^{\circ}C$ show hexagonal structured YMnO$_3$. However, the film annealed in oxygen ambient shows poor crystallinity, and the second phase as $Y_2$O$_3$ and orthorhombic-YMnO$_3$ were shown. The annealing ambient and pressure on the crystallinity of YMnO$_3$ thin films is very important. The C-V characteristics have a hysteresis curve with a clockwise rotation, which indicates ferroelectric polarization switching behavior. When the gate voltage sweeps from +5 to 5 V, the memory window of the Pt/YMnO$_3$/Y$_2$O$_3$/Si gate capacitor annealed at 85$0^{\circ}C$ is 1.8 V. The typical leakage current densities of the films annealed in oxygen and vacuum ambient are about 10$^{-3}$ and 10$^{-7}$ A/cm$^2$ at applied voltage of 5 V.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.605-610
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• 2010

The devices based on electrically erasable programmable read-only memory (EEPROM) structure are proposed for the detection of external electric charges. A large size charge contact window (CCW) extended from the floating gate is employed to immobilize external charges, and a control gate with stacked metal-insulator-metal (MIM) capacitor is adapted for a standard single polysilicon CMOS process. When positive voltage is applied to the capacitor of CCW of an n-channel EEPROM, the drain current increases due to the negative shift of its threshold voltage. Also when a pre-charged external capacitor is directly connected to the floating gate metal of CCW, the positive charges of the external capacitor make the drain current increase for n-channel, whereas the negative charges cause it to decrease. For an p-channel, however, the opposite behaviors are observed by the external voltage and charges. With the attachment of external charges to the CCW of EEPROM inverter, the characteristic inverter voltage behavior shifts from the reference curve dependent on external charge polarity. Therefore, we have demonstrated that the EEPROM inverter is capable of detecting external immobilized charges on the floating gate. and these devices are applicable to sensing the pH's or biomolecular reactions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 한국세라믹학회지
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• 제42권2호
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• pp.104-109
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• 2005

PbO 완충층의 역할을 확인하기 위해, r.f. magnetron sputtering법을 이용하여 p-type (100) Si 기판 위에 $Pt/Pb_{1.1}Zr_{0.53}Ti_{0.47}O_{3}$와 PbO target으로 Pt/PZT/PbO/Si의 MFIS 구조를 제조하였다. MFIS 구조에 완충층으로 PbO를 삽입함으로써 PZT 박막의 결정성이 크게 향상되었고, 박막의 공정온도도 상당히 낮출 수 있었다. 그리고 XPS depth profile 분석 결과, PbO 증착시 기판온도가 PbO와 Si의 계면에서 Pb의 확산에 미치는 영향을 확인하였다. PbO 완충층을 삽입한 MFIS는 높은 메모리 윈도우와 낮은 누설전류 밀도를 가지는 추수한 전기적 특성을 나타내었다. 특히, 기판온도 $300^{\circ}C$에서 증착된 PbO를 삽입한 Pt/PZT(200nm, $400^{\circ}C)PbO(80nm)/Si$는 9V의 인가전압에서 2.OV의 가장 높은 메모리 윈도우 값을 나타내었다.