• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• The Korean Journal of Physiology and Pharmacology
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• v.26 no.6
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• pp.415-425
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• 2022

Memory formation in the hippocampus is formed and maintained by circadian clock genes during sleep. Sleep deprivation (SD) can lead to memory impairment and neuroinflammation, and there remains no effective pharmacological treatment for these effects. Myricetin (MYR) is a common natural flavonoid that has various pharmacological activities. In this study, we investigated the effects of MYR on memory impairment, neuroinflammation, and neurotrophic factors in sleep-deprived rats. We analyzed SD-induced cognitive and spatial memory, as well as pro-inflammatory cytokine levels during SD. SD model rats were intraperitoneally injected with 10 and 20 mg/kg/day MYR for 14 days. MYR administration significantly ameliorated SD-induced cognitive and spatial memory deficits; it also attenuated the SD-induced inflammatory response associated with nuclear factor kappa B activation in the hippocampus. In addition, MYR enhanced the mRNA expression of brain-derived neurotropic factor (BDNF) in the hippocampus. Our results showed that MYR improved memory impairment by means of anti-inflammatory activity and appropriate regulation of BDNF expression. Our findings suggest that MYR is a potential functional ingredient that protects cognitive function from SD.

• Asia-Pacific Journal of Business
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• v.13 no.2
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• pp.23-37
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• 2022

Purpose - The purpose of this paper is to analyze the dynamic factors of the daily FX implied volatility based on the fractional integration methods focusing on long memory feature and structural changes. Design/methodology/approach - This paper uses the daily FX implied volatility data of the EUR-USD and the JPY-USD exchange rates. For the fractional integration analysis, this paper first applies the basic ARFIMA-FIGARCH model and the Local Whittle method to explore the long memory feature in the implied volatility series. Then, this paper employs the Adaptive-ARFIMA-Adaptive-FIGARCH model with a flexible Fourier form to allow for the structural changes with the long memory feature in the implied volatility series. Findings - This paper finds statistical evidence of the long memory feature in the first two moments of the implied volatility series. And, this paper shows that the structural changes appear to be an important factor and that neglecting the structural changes may lead to an upward bias in the long memory feature of the implied volatility series. Research implications or Originality - The implied volatility has widely been believed to be the market's best forecast regarding the future volatility in FX markets, and modeling the evolution of the implied volatility is quite important as it has clear implications for the behavior of the exchange rates in FX markets. The Adaptive-ARFIMA-Adaptive-FIGARCH model could be an excellent description for the FX implied volatility series

• ETRI Journal
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• v.34 no.3
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• Electronics and Telecommunications Trends
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• v.39 no.1
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• pp.62-73
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• 2024

Artificial intelligence relies on data-driven analysis, and the data processing performance strongly depends on factors such as memory capacity, bandwidth, and latency. Fast and large-capacity memory can be achieved by composing numerous high-performance memory units connected via high-performance interconnects, such as Compute Express Link (CXL). CXL is designed to enable efficient communication between central processing units, memory, accelerators, storage, and other computing resources. By adopting CXL, a composable computing architecture can be implemented, enabling flexible server resource configuration using a pool of computing resources. Thus, manufacturers are actively developing hardware and software solutions to support CXL. We present a survey of the latest software for CXL memory utilization and the most recent CXL memory emulation software. The former supports efficient use of CXL memory, and the latter offers a development environment that allows developers to optimize their software for the hardware architecture before commercial release of CXL memory devices. Furthermore, we review key technologies for improving the performance of both the CXL memory pool and CXL-based composable computing architecture along with various use cases.

• Biomolecules & Therapeutics
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• v.21 no.3
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• pp.229-233
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• 2013

This study was aimed at investigating the possible effects of phytoceramide (Pcer) on learning and memory and their underlying mechanisms. Phytoceramide was orally administered to ICR mice for 7 days. Memory performances were assessed using the passive avoidance test and Y-maze task. The expressions of phosphorylated cAMP response element binding protein (pCREB), brain-derived neurotrophic factor (BDNF) were measured with immunoblot. The incorporation of 5-bromo-2-deoxyuridine (BrdU) in hippocampal regions was investigated by using immunohistochemical methods. Treatment of Pcer enhanced cognitive performances in the passive avoidance test and Y-maze task. Immunoblotting studies revealed that the phosphorylated CREB and BDNF were significantly increased on hippocampus in the Pcer-treated mice. Immunohistochemical studies showed that the number of immunopositive cells to BrdU was significantly increased in the hippocampal dentate gyrus regions after Pcer-treatment for 7 days. These results suggest that Pcer contribute to enhancing memory and BDNF expression and it could be secondary to the elevation of neurogenesis.

• Journal of Microbiology and Biotechnology
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• v.21 no.8
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• pp.874-883
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• 2011

Many studies have shown that the steamed root of Rehmannia glutinosa (SRG), which is widely used in the treatment of various neurodegenerative diseases in the context of Korean traditional medicine, is effective for improving cognitive and memory impairments. The purpose of this study was to examine whether SRG extracts improved memory defects caused by administering scopolamine (SCO) into the brains of rats. The effects of SRG on the acetylcholinergic system and proinflammatory cytokines in the hippocampus were also investigated. Male rats were administered daily doses of SRG (50, 100, and 200 mg/kg, i.p.) for 14 days, 1 h before scopolamine injection (2 mg/kg, i.p.). After inducing cognitive impairment via scopolamine administration, we conducted a passive avoidance test (PAT) and the Morris water maze (MWM) test as behavioral assessments. Changes in cholinergic system reactivity were also examined by measuring the immunoreactive neurons of choline acetyltransferase (ChAT) and the reactivity of acetylcholinesterase (AchE) in the hippocampus. Daily administration of SRG improved memory impairment according to the PAT, and reduced the escape latency for finding the platform in the MWM. The administration of SRG consistently significantly alleviated memory-associated decreases in cholinergic immunoreactivity and decreased interleukin-$1{\beta}$ (IL-$1{\beta}$) and tumor necrosis factor-${\alpha}$ (TNF-${\alpha}$) mRNA expression in the hippocampus. The results demonstrated that SRG had a significant neuroprotective effect against the neuronal impairment and memory dysfunction caused by scopolamine in rats. These results suggest that SRG may be useful for improving cognitive functioning by stimulating cholinergic enzyme activities and alleviating inflammatory responses.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.