• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of Digital Convergence
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• v.11 no.7
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• pp.297-304
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• 2013

This research explores the effect of TV news camerawork and viewers' involvement on memory of news through experiment. For this experimental research, 2 groups of subjects composed of university students were exposed to different types of TV news and responded to survey questions which were analysed by SPSS program. This research found that camerawork of TV news doesn't have an effect on short-term memory but on long-term memory. Though the fact viewers' involvement has a positive effect on shot-term and long-term memory was found, interactive effect of viewers' involvement and camerawork as an peripheral clue was not found.

• Journal of Korea Spatial Information System Society
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• v.11 no.2
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• pp.79-88
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• 2009

The volume of memory to store real-time data stream is varied dynamically. Continuous queries processing the data stream must manage the storage volume dynamically. In previous research, according to current volume of data a general memory manager which allocates and releases memory by a page unit is researched.However, the method frequently executes page allocation and release to store data stream. Moreover, particularly delayed queries can monopolize many of pages because the method directly allocates pages when a query has not enough memory. Focusing on the problems in memory management systems, this research proposes a memory management method which reduces the frequency of allocation and release and uniformly distributes pages for queries. The method can reduce the frequency of allocation and release through allocation based on utilization ratio of pages in each query and prevent memory monopoly through memory allocation which considers query delay.

• Proceedings of the KSRS Conference
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• v.2
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• pp.725-727
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• 2006

The development of GIS and Location-Based Services requires a high-level database that will be able to allow real-time access to moving objects for spatial and temporal operations. MODB.MM is able to meet these requirements quite adequately, providing operations with the abilities of acquiring, storing, and querying large-scale moving objects. It enables a dynamic and diverse query mechanism, including searches by region, trajectory, and temporal location of a large number of moving objects that may change their locations with time variation. Furthermore, MODB.MM is designed to allow for performance upon main memory and the system supports the migration on out-of-date data from main memory to disk. We define the particular query for truncation of moving objects data and design two migration methods so as to operate the main memory moving objects database system and file-based location storage system with.

• Atmosphere
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• v.22 no.1
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• pp.109-115
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• 2012

We parallelized the CFD_NIMR model, which is a numerical meteorological model, for best performance on both of distributed and shared memory parallel computers. This hybrid parallelization uses MPI (Message Passing Interface) to apply horizontal 2-dimensional sub-domain out of the 3-dimensional computing domain for distributed memory system, as well as uses OpenMP (Open Multi-Processing) to apply vertical 1-dimensional sub-domain for utilizing advantage of shared memory structure. We validated the parallel model with the original sequential model, and the parallel CFD_NIMR model shows efficient speedup on the distributed and shared memory system.

• Toxicological Research
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• v.24 no.3
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• pp.183-188
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• 2008

The behavioral phenotypes of out-bred ICR mice were compared with those of in-bred C57BL/6 and BALB/c mice. In particular, this study examined the locomotor activity and two forms of hippocampus-dependent learning paradigms, passive avoidance and object recognition memory. The basal open-field activity of the ICR strain was greater than that of the C57BL/6 and BALB/c strains. In the passive avoidance task, all the mice showed a significant increase in the cross-over latency when tested 24 hours after training. The strength of memory retention in the ICR mice was relatively weak and measurable, as indicated by the shorter cross-over latency than the C57BL/6 and BALB/c mice. In the object recognition memory test, all strains had a significant preference for the novel object during testing. The index for the preference of a novel object was lower for the ICR and BALB/c mice. Nevertheless, the variance and the standard deviation in these strains were comparable. Overall, these results confirm the strain differences on locomotor activity and hippocampus-dependent learning and memory in mice.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1635-1641
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• 2011

In this paper, we research the method for HDD I/O Performance improvement by Filter Driver & NAND FLASH Memory. This paper was started from NAND Flash Memory can not be replaced by HDD because of high cost. So We consider that using NAND Flash Memory as cache for HDD. It can be achieved high HDD Performance through Filter Driver by low cost.