• Title/Summary/Keyword: Memory reduction

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A Light Weighted Robust Korean Morphological Analyzer for Korean-to-English Mobile Translator (한영 모바일 번역기를 위한 강건하고 경량화된 한국어 형태소 분석기)

  • Yuh, Sang-Hwa
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.2
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    • pp.191-199
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    • 2009
  • In this paper we present a light weighted robust Korean morphological analyzer for mobile devices such as mobile phones, smart phones, and PDA phones. Such mobile devices are not suitable for natural language interfaces for their low CPU performance and memory restriction. In order to overcome the difficulties we propose 1) an online analysis by using Key Event Handler mechanism, 2) and a robust analysis of the Korean sentences with spacing errors without its correction pre-processing. We adapt the proposed Korean analyzer to a Korean-English mobile translator, which shows 5.8% memory usage reduction and 19.0% enhancement of average response time.

Analysis of Improvement on Delay Failures in Separated Driving-line Sense Amplifier (구동라인분리 센스앰프의 딜레이페일 개선 효과에 대한 분석)

  • Dong-Yeong Kim;Su-Yeon Kim;Je-Won Park;Sin-Wook Kim;Myoung Jin Lee
    • Journal of IKEEE
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    • v.28 no.1
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    • pp.1-5
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    • 2024
  • To improve the performance of DRAM, it is essential to reduce sensing failures caused by mismatch in SA. Unlike flip failures, delay failures can be degraded, especially when high-speed operation is required, making it a critical consideration in the design of next-generation memory. While conventional SA operates with all transistors starting amplification simultaneously, SDSA selectively activates only two transistors that output BLB, thus alleviating offset. In this paper, we validate the superior performance of SDSA in mitigating delay failures through simulations. It was confirmed that SDSA exhibits approximately a 90 % reduction in delay failures compared to conventional SA.

NVM-based Write Amplification Reduction to Avoid Performance Fluctuation of Flash Storage (플래시 스토리지의 성능 지연 방지를 위한 비휘발성램 기반 쓰기 증폭 감소 기법)

  • Lee, Eunji;Jeong, Minseong;Bahn, Hyokyung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.4
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    • pp.15-20
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    • 2016
  • Write amplification is a critical factor that limits the stable performance of flash-based storage systems. To reduce write amplification, this paper presents a new technique that cooperatively manages data in flash storage and nonvolatile memory (NVM). Our scheme basically considers NVM as the cache of flash storage, but allows the original data in flash storage to be invalidated if there is a cached copy in NVM, which can temporarily serve as the original data. This scheme eliminates the copy-out operation for a substantial number of cached data, thereby enhancing garbage collection efficiency. Experimental results show that the proposed scheme reduces the copy-out overhead of garbage collection by 51.4% and decreases the standard deviation of response time by 35.4% on average.

Method of Fast Interpolation of B-Spline Volumes for Reconstructing the Heterogeneous Model of Bones from CT Images (CT 영상에서 뼈의 불균질 모델 생성을 위한 B-스플라인 볼륨의 빠른 보간 방법)

  • Park, Jun Hong;Kim, Byung Chul
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.40 no.4
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    • pp.373-379
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    • 2016
  • It is known that it is expedient to represent the distribution of the properties of a bone with complex heterogeneity as B-spline volume functions. For B-spline-based representation, the pixel values of CT images are interpolated by B-spline volume functions. However, the CT images of a bone are three-dimensional and very large, and hence a large amount of memory and long computation time for the interpolation are required. In this study, a method for resolving these problems is proposed. In the proposed method, the B-spline volume interpolation problem is simplified by using the uniformity of pixel spacing of the image and the properties of B-spline basis functions. This results in a reduction in computation time and the amount of memory used. The proposed method was implemented and it was verified that the computation time and the amount of memory used were reduced.

Forsythiaside, a Constituent of the Fruits of Forsythia suspense, Ameliorates Scopolamine-Induced Memory Impairment in Mice

  • Kim, Sun-Ho;Kim, Dong-Hyun;Choi, Ji-Joung;Lee, Jong-Gu;Lee, Choong-Ho;Park, Se-Jin;Jung, Won-Yong;Park, Dong-Hyun;Ko, Kwang-Ho;Lee, Seung-Ho;Ryu, Jong-Hoon
    • Biomolecules & Therapeutics
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    • v.17 no.3
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    • pp.249-255
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    • 2009
  • Forsythiaside is a polyphenolic constituent of the fruits of Forsythia suspense Vahl which are widely used as anti-inflammatory herbal raw materials in traditional Chinese medicine. In the present study, the authors assessed the effects of forsythiaside on learning and memory impairments induced by scopolamine using a passive avoidance and the Morris water maze tests in mice. Drug-induced amnesia was induced by scopolamine treatment (1 mg/kg, i.p.). Forsythiaside (10 mg/kg, p.o) administration significantly prevented scopolamine-induced step-through latency reduction in the passive avoidance test and scopolamine-induced increased escape latency in the Morris water maze test (p<0.05). Moreover, in an ex-vivo study, forsythiaside treatment (10 mg/kg, p.o) significantly reduced the increase of thiobarbituric acid reactive substance levels induced by scopolamine (p<0.05). Taken together, the present study suggests that forsythiaside could be useful for the treatment of cognitive impairment, and that its beneficial effects are mediated, in part, by its antioxidative properties.

Embedded Compression Codec Algorithm for Motion Compensated Wavelet Video Coding System (움직임 보상된 웨이블릿 기반의 비디오 코딩 시스템에 적용 가능한 임베디드 압축 코덱 알고리즘)

  • Kim, Song-Ju
    • The Journal of the Korea Contents Association
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    • v.12 no.3
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    • pp.77-83
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    • 2012
  • In this paper, a low-complexity embedded compression (EC) Codec algorithm for the wavelet video coder is applied to reduce excessive external memory requirements. The EC algorithm is used to achieve a fixed compression ratio of 50 % under the near-lossless-compression constraint. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform stages compared with direct implementation of the wavelet video encoder of this paper. Furthermore, the EC scheme based on a forward adaptive quantization and fixed length coding can save bandwidth and size of buffer between DWT and SPIHT to 50 %. Simulation results show that our EC algorithm present only PSNR degradation of 0.179 and 0.162 dB in average when the target bit-rate of the video coder are 1 and 0.5 bpp, respectively.

A Generator of 64~8,192-point FFT/IFFT Cores with Single-memory Architecture for OFDM-based Communication Systems (OFDM 기반 통신 시스템용 단일 메모리 구조의 64~8,192점 FFI/IFFFT 코어 생성기)

  • Yeem, Chang-Wan;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.205-212
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    • 2010
  • This paper describes a core generator (FCore_Gen) which generates Verilog-HDL models of 640 different FFT/IFFT cores with selected parameter value for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed m $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

A Design of LDPC Decoder for IEEE 802.11n Wireless LAN (IEEE 802.11n 무선 랜 표준용 LDPC 복호기 설계)

  • Jung, Sang-Hyeok;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.5
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    • pp.31-40
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    • 2010
  • This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

Low-Power IoT Microcontroller Code Memory Interface using Binary Code Inversion Technique Based on Hot-Spot Access Region Detection (핫스팟 접근영역 인식에 기반한 바이너리 코드 역전 기법을 사용한 저전력 IoT MCU 코드 메모리 인터페이스 구조 연구)

  • Park, Daejin
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.2
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    • pp.97-105
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    • 2016
  • Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

Neuroprotective Effects of the Extracts from the Aerial Parts of Carthamus tinctorius L. on Transient Cerebral Global Ischemia in Rats (홍화 지상부 추출물의 전뇌허혈에 대한 신경보호 효과)

  • Kim, Young Ock;Lee, Sang Won;Yang, Seung Ok;Na, Sae Won;Kim, Su Kang;Chung, Joo Ho
    • Korean Journal of Medicinal Crop Science
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    • v.22 no.1
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    • pp.46-52
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    • 2014
  • In traditional Korean and Chinese medicine, safflower (Carthamus tinctorius L.) for the treatment of central nervous system-related symptoms such as tremor, seizure, stroke and epilepsy. We investigated the effects of safflower could influence cerebral ischemia-induced neuronal and cognitive impairments. Administration of safflower for 1 day (200 mg/kg body weight, p.o.) increased the survival of hippocampal CA1 pyramidal neurons after transient global brain ischemia. And neurological functions measured as short term memory. Post-treatment with safflower for 2 times decreased the induction/reduction - induced production of neuronal cell loss from global cerebral ischemia. Safflower markedly decreased neuronal cell death and also caused a decrease in the content of thiobarbituric acid-reacting substances (TBARS) ($55.2{\pm}9.4{\mu}mol\;mg^{-1}$) and significant improvement of activities of glutathione (GSH) ($27.2{\pm}5.0{\mu}mol\;mg^{-1}$) in hippocampus. We conclude that treatment with safflower attenuated learning and memory deficits, and neuronal cell loss induced by global cerebral ischemia. These results suggest that safflower may be a potential candidate for the treatment of vascular dementia.