• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Smart Structures and Systems
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• 제18권4호
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• pp.663-682
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• 2016

Continuum manipulators as a kind of mechanical arms are useful tools in special robotic applications. In medical applications, like colonoscopy, a maneuverable thin and flexible manipulator is required. This research is focused on developing a basic module for such an application using shape memory alloys (SMA). In the structure of the module three wires of SMA are uniformly distributed and attached to the circumference of a flexible tube. By activating wires, individually or together, different rotation regimes are provided. SMA model is used based on Brinson work. The SMA model is combined to model of flexible tube to provide a composite model of the module. Simulating the model in Matlab provided a platform to be used to develop controller. Complex and nonlinear behavior of SMA make the control problem hard especially when a few SMA actuators are active simultaneously. In this paper, position control of the two degree of freedom module is under focus. An experimental control strategy is developed to regulate a desired position in the module. The simulation results present a reasonable performance of the controller. Moreover, the results are verified through experiments and show that the continuum module of this paper would be used in real modular manipulators.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.507-511
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• 2010

Digital radio frequency memory (이하 DRFM)은 입력되는 RF신호를 저장 후 필요한 시점에 입력된 RF신호로 복원하여 출력하는 기능을 가진 장치로써 Jammer, EW시뮬레이터, Target Echo Generator 등 사용되는 분야가 광범위하다. 본 논문에서는 고주파 입/출력모듈, 국부 발진모듈로 구성된 고주파부와 디지털 처리부로 이루어진 DRFM의 하드웨어적 구현 방안을 제안한다. 그리고 펄스형태의 RF신호를 양자화하는 ADC(A/D conversion), 이 데이터를 저장하고 재생신호를 생산하는 FPGA와 RF 신호를 생산하는 DAC(D/A conversion)로 구성되는 디지털 처리부에서 복제된 신호 생성방안을 제안한다. 이렇게 제안된 방안을 적용하여 제작한 후 모의 신호를 입력하여 얻은 시험결과를 통하여 이 제안방안의 타당성을 확인한다.

• 한국콘텐츠학회논문지
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• 제10권6호
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• pp.80-90
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• 2010

본 논문에서는 홈 네트워크 환경에서 서비스 이동성을 지원하기 위한 에이전트 구현 방안을 제안한다. 에이전트 구현을 위해 단말 에이전트와 서버 에이전트의 설계 방안을 서술하였다. 구체적으로 단말 에이전트의 사용자 인식 모듈, 시그널링 메시지 수신 및 파싱 모듈과 서버 에이전트의 시그널링 메시지 수신 및 파싱 모듈, 멀티미디어 스위칭 모듈, 메모리 관리 모듈에 대한 설계 방안을 서술하였다. 또한 사용자의 위치 관리를 위해 IP 공유기에서 관리되어야 할 파라메터를 정의하였고 이 파라메터들이 메모리에 저장될 바인딩 테이블의 구조를 설계하였다. 성능 분석을 위해서 M/M/1/K 큐잉 모델을 이용하여 메모리 크기, 차단 확률, 활용도 간의 관계를 도출하였다. 얻어진 결과로부터 서버에이전트가 탑재되는 IP 공유기에서 요구되는 메모리의 크기를 예측할 수 있음을 보였다.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2010년도 춘계학술대회 논문집
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• pp.572-573
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• 2010

Vibration analysis of Fine-pitch Ball Grid Array (FBGA) packages mounted on a Printed Circuit Board (PCB) subjected to harmonic excitation is performed by using finite element method (FEM). A finite element model of a memory module is composed of three main parts, packages, simplified solder balls and bare PCB. At first, natural frequencies and mode shapes of the developed model were confirmed experimentally. Secondly, the harmonic excitation experiment for the module was carried out at the first natural frequency of the memory module, and it was verified with the simulation by using mode superposition method at a constant acceleration.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• 대한전자공학회논문지SP
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• 제41권6호
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• pp.231-237
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• 2004

본 논문은 디지털 TV의 다양한 분야로의 확장을 위해서 디지털 TV에 접목하는 멀티미디어 부가기능 모듈 및 관련 인터페이스 개발에 관한 것이다. 이 부가기능 모듈은 디지털 TV 시스템에 장착되며 디지털 카메라, 캠코더, PC로 저장한 정지 영상을 TV 화면으로 디스플레이 해주는 기능을 수행한다. 본 시스템은 현재 디지털 카메라 등에서 널리 사용되고 있는 5 종류의 메모리 카드를 지원 하도록 하였으며 JPEG, BMP, TIFF의 3가지 영상 포맷을 지원한다. 또한 아날로그 RGB 출력으로 HD(High Definition)급부터 WXGA(Wide Extended Graphics Array) 급까지 지원하여 광범위한 디지털 TV 세트에 적용이 가능하다.