• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.237-240
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• 2003

Efficient memory management is one of the most crucial requirement of lava virtual machine. In Java, memory is allocated everytime when a new instance of class is created or when a method is called. The allocated memory is freed when the instance is no longer used, or when the called method is returned. In this paper we have examined the memory management scheme applied to the simpleRTJ lava virtual machine. The simpleRTJ has such a distinguished characteristic in its memory management scheme that the size of all instances are forced to be the same and the size of stack frames of all methods be the same, respectively. We present in this paper the scheme thoroughly and analyze its anticipated performance qualitatively.

• Journal of KIISE
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• v.42 no.8
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• pp.972-978
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• 2015

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.8
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• pp.378-384
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• 2008

Many embedded systems are supporting Java as their software platform via Java virtual machine. Java virtual machine manages memory automatically by providing automatic memory management, i.e. garbage collector. Because only scarce memory is available to embedded system, Java virtual machine should use small memory and manage it efficiently. This paper introduces two memory management techniques to exploit small memory in Java virtual machine which can execute multiple Java applications concurrently. First, compaction based garbage collection is introduced to overcome external fragmentation problem in presence of immovable memory area. Then garbage collector driven class unloading is introduced to reduce memory use of unnecessary loaded classes. We implemented these techniques in working embedded system and observed that they are very efficient, since more Java applications are able to be executed concurrently and memory use is also reduced with these techniques.

• ETRI Journal
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• v.26 no.1
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• pp.21-26
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• 2004

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.865-868
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• 2001

TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.499-501
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• 2003

As semiconductor memory becomes cheaper, the memory capacity of computer system is increasing. Therefore computer system has sufficient memory for a plentiful spatial data. With emerging spatial application required high performance, this paper presents a GIS database system in main memory. Memory residence can provide both functionality and performance for a database management system. This paper describes design of DBMS for storing, querying, managing and analyzing for spatial and non-spatial data in main-memory. This memory resident GIS DBMS supports SQL for spatial query, spatial data model, spatial index and interface for GIS tool or applications.

• Journal of Information Processing Systems
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• v.11 no.3
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• pp.389-405
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• 2015

Most traditional database systems exploit a record-oriented model where the attributes of a record are placed contiguously in a hard disk to achieve high performance writes. However, for read-mostly data warehouse systems, the column-oriented database has become a proper model because of its superior read performance. Today, flash memory is largely recognized as the preferred storage media for high-speed database systems. In this paper, we introduce a column-oriented database model based on flash memory and then propose a new column-aware flash indexing scheme for the high-speed column-oriented data warehouse systems. Our index management scheme, which uses an enhanced $B^+$-Tree, achieves superior search performance by indexing an embedded segment and packing an unused space in internal and leaf nodes. Based on the performance results of two test databases, we concluded that the column-aware flash index management outperforms the traditional scheme in the respect of the mixed operation throughput and its response time.

• Journal of KIISE:Databases
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• v.36 no.1
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• pp.1-7
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• 2009

Flash memory has its unique characteristics: i.e., (1) the write operation is much more costly than the read operation. (2) In-place updating is not allowed. In this paper, we first analyze how these characteristics affect the performance of record management in flash memory, and discuss the problems with previous methods for record management when they are applied to flash memory environment. Next, we propose a new record management method to be suitable for flash memory environment. The proposed method employs a new concept of a container that makes it possible to overwrite data on flash memory several times when performing insertions, deletions, and modifications of records. As a result, this method reduces the number of overwrite operations, and consequently does the number of erase operations. The results of experiments show that our method improves the performance by up to 34%, compared with the previous one.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.39-42
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• 2001

This paper proposes the design technique of memory sparing to overcome memory hard error Memory Sparing is used to increase the reliability and availability of commercial, military and space computer such as a Data Server, Communication Server, Flight Computer in airplane and On-Board Computer in spacecraft. But the documents about this technique are rare and hard to find. This paper has some useful information about memory error correction and memory error management.