• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 센서 박막재료 반도체재료 기술교육
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• pp.107-110
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• 2002

The optical memory devices of BST thin films to composite $(Ba_{0.7}\;Sr_{0.3})TiO_{3}$ using sol-gel method were fabricated by changing of the depositing layer number on $Pt/Ti/SiO_{2}/Si$ substrate. The structural properties of optical memory devices to be ferroelectric was investigated by fractal analysis and 3-dimension image processing. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was $2500[\AA]$, $3500[\AA]$ and $3800[\AA]$. BST thin films exhibited the most pronounced grain growth. The surface morphology image was roughness with coating numbers. The thin films increasing with coating numbers shows a more textured and complex configuration.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
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• pp.252-258
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• 1995

The purpose of this study is to provide the integrated process control system, utilizing neural network modeling, to search for the appropriate choice input, and to keep the process output within the desired rang in the real etch process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.339-342
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• 1988

Typical magnetic bubble propagation failure modes of ion implanted magnetic bubble computer memory devices were observed and their failure mechanisms were analize. The skidding failure mode is due to the pushing of a strong repulsive charged wall. If this pushing is stronger than the edge affinity of the bubble in the cusp, the bubble moves out of the cusp when it is supposed to stay there. The stripeout failure modes across the adjacent track or along the track can be explained by considering the relative strength of the charged wall and the edge affinity encountered by both ends of the stripe. The skipping of the first cusp of a track is believed to be due to the whipping motion of the charged wall. The bubble moves directly to the second cusp via the long charged wall pointing to the second cusp skipping the first cusp.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• 한국전자통신학회논문지
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• 제4권4호
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• pp.301-305
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• 2009

Pt 나노입자의 합성과 이를 이용한 hybrid Pt-$SiO_2$ 나노입자의 합성을 성공적으로 수행하였으며, self-assembled Pt nanoparticles monolayer를 charge trapping layer로 활용하는 metal-oxide-semiconductor(MOS) type memory의 한 예로 non-volatile memory(NVM)의 응용을 보임으로써 나노입자의 활용 가능성을 보이고, 또한, hybrid Pt-$SiO_2$ 나노입자 박막 층의 제어를 통한 MOS type memory device에의 보다 더 넓은 활용 가능성을 보이고자 하였다.

• 한국컴퓨터정보학회논문지
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• 제22권5호
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• pp.1-9
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• 2017

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.

• 한국진공학회지
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• 제17권4호
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• pp.253-261
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• 2008

Programmable metalization cell (PMC) memory 소자로도 명명되는 고체 전해질 메모리 소자는 비휘발성, 고속 및 높은 ON/OFF 저항비 등을 갖고 있기 때문에, 차세대 비휘발성 메모리로서 각광받고 있는 소자 중의 하나이다. 본 논문에서는 고체 전해질 메모리 소자의 동작 원리를 먼저 소개하고자 한다. 또한, 메모리향 소자 개발을 진행 중인 미국 코지키 교수 그룹, 비메모리향 소자 개발을 진행 중인 일본 NEC 그룹 등의 해외 연구진과, Te 계열의 칼코게나이드 합금을 채택하여 소자를 제작한 한국전자통신연구원 및 충남대학교 등의 국내 연구진의 연구 성과를 소개하고자 한다.