• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.429-432
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• 1998

The impact of hot carrier induced gate leakage current on the refresh time of memory devices has been examined. The maximum allowable supply voltage for cell transistor has been determined form the degradation of the refresh time. The desing guideline for cell capacitors and refresh circuits has been suggested.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.82-82
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• 2005

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.11a
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• pp.73-73
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• 1998

• Applied Chemistry for Engineering
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• v.23 no.6
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• pp.515-520
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• 2012

In this review, the fabrication of silicon based memory capacitor and organic memory thin film transistors (TFTs) was discussed for their potential identification tag applications and biosensor applications. Metal or non-metal nanoparticles (NPs) could be capped with chemicals or biomolecules such as protein and oligo-DNA, and also be self-assembly monolayered on corresponding target biomolecules conjugated dielectric layers. The monolayered NPs were formed to be charging elements of a nano floating gate layer as forming organic memody deivces. In particular, the strong and selective binding events of the NPs through biomolecular interactions exhibited effective electrostatic phenomena in memory capacitors and TFTs formats. In addition, memory devices fabricated as organic thin film transistors (OTFTs) have been intensively introduced to facilitate organic electronics era on flexible substrates. The memory OTFTs could be applicable eventually to the development of new conceptual devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.160-160
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• 2003

This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 $\mu\textrm{m}$) dynamic random access memory (DRAM) devices. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 $\mu\textrm{m}$ and thus the storage node electrode with the CD of 0.15 $\mu\textrm{m}$ could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmount the above difficulties. The Ru electrode for the stack-type structure is introduced and alternative schemes based on the introduction of the concave-type structure using Pt or Ru as an electrode material are outlined.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1401-1405
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• 2010

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $HfO_2$/p-Si structures. The $HfO_2$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. TEMAHf and $H_2O$ were used as the hafnium and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TEMAHf pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $HfO_2$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2420-2424
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• 2009

We have successfully demonstrated of metal-insulator-semiconductor (MIS) capacitors with $Al_2O_3/p-Si$ structures. The $Al_2O_3$ film was grown at $200^{\circ}C$ on H-terminated Si wafer by atomic layer deposition (ALD) system. Trimethylaluminum [$Al(CH_3)_3$, TMA] and $H_2O$ were used as the aluminum and oxygen sources. A cycle of the deposition process consisted of 0.1 s of TMA pulse, 10 s of $N_2$ purge, 0.1 s of $H_2O$ pulse, and 60 s of $N_2$ purge. The 5 nm thick $Al_2O_3$ layer prepared on Si substrate by ALD exhibited excellent electrical properties, including low leakage currents, no mobile charges, and a good interface with Si.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.725-728
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• 2000

Ferroelectric thin film capacitors with high dielectric constant are important for the application of memory devices. In this work, We have systematically investigated the variation of grain sizes depending on the process condition of two-step process. Both in-situ annealing and ex-annealing have been compared depending on the annealing time. C-V measurement, ferroelectric properties, leakage current, XRD and SEM were performed to investigate the electircal properties and microstructural properties of Pb(La, Ti)O$_3$ films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.861-864
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• 2000

Ferroelectric thin film capacitors with high dielectric constant are important for the application of memory devices. In this work, thin films of PLT(28)(Pb$\sub$0.72/La$\sub$0.28/Ti$\sub$0.93/O$_3$) were fabricated on Pt/Ti/SiO$_2$/Si substrates in-situ annealing and ex-situ annealing have been compared depending on the annealing time. We have systematically investigated the variation of grain sizes depending on the condition of post-annealing and the variation of deposition rate. C-V measurement, ferroelectric properties, leakage current and SEM were performed to investigate the electrical properties and the microstructural properties of Pb(La,Ti)O$_3$.

• Journal of the Korean Applied Science and Technology
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• v.35 no.4
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• pp.1206-1212
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• 2018

In this study, the polarization reversal characteristics of thin film capacitors with a thickness of 100 nm or less fabricated with ferroelectric polymer were measured and analyzed. For the fixed film thickness, polarization reversal occurred at higher coercive fields as the applied maximum electric field increased. For the fixed maximum electric field, polarization reversal occurred at the same coercive field irrespective of the thickness of the thin film. The proportional constant values between the logarithmic electric field and the logarithmic scale frequency were $0.12{\pm}0.01$ for all measurements. As a result, the ferroelectric polymer capacitors consistently exhibited polarization reversal characteristics without any size effects up to a thickness of 40 nm. This study shows the possibility of a polymer memory device that can operate at low voltage, which is useful for predicting the behavior of a low-voltage operating polymer memory device.