• 한국산학기술학회논문지
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• 제10권5호
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• pp.942-946
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• 2009

ISP와 JPEG 인코더 사이에는 라스터 스캔 순서의 데이터를 $8{\times}8$ 블록 스캔 순서로 변환하는 스캔 순서 변환기가 위치한다. 최근에 단일 라인 메모리를 사용함으로써, 하드웨어 규모를 감축한 스캔 순서 변환기가 제안되었으나 매 사이클마다 기입과 독출 동작을 수행함에 따라서 전체 전력 예산의 대부분을 SRAM이 소모하는 문제점을 야기했다. 본 논문에서는 SRAM에 대한 억세스 빈도를 술이기 위하여 데이터 packer와 unpacker를 스캔 순서 변환 과정에 삽입함으로써, SRAM에 대한 억세스 빈도를 1/8로 줄이는 구조를 제안한다. 실험결과, 제안한 구조를 적용할 경우 SXGA 해 상도에서의 SRAM 전력소모량을 16% 이하로 줄어든다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2017년도 추계학술발표대회
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• pp.679-681
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• 2017

Apache Storm은 대용량 데이터 스트림을 처리하기 위한 실시간 분산 병렬 처리 프레임워크이며, 이를 사용해 다수의 프로세스 및 스레드를 동시에 동작시킬 수 있다. 하지만, 이러한 멀티 프로세스 및 스레드 환경을 제공하는 Storm은 많은 네트워크 시스템 호출을 수행하고, 이는 잦은 문맥 전환(context switch), 운영체제로의 버퍼 복사, 운영체제 내의 버퍼 복사 등으로 인해 CPU 과부하 문제를 발생시킬 수 있다. 이러한 문제는 고성능 네트워크 장비인 InfiniBand의 IPoIB(IP over InfiniBand) 통신을 사용할 때, InfiniBand가 지원하는 대역폭(bandwidth) 대비 저용량 데이터의 송수신으로 인해 더 잦은 문맥 전환과 버퍼 복사가 발생하여 CPU 과부하 문제가 더욱 심각해진다. 따라서, 본 논문에서는 InfiniBand의 RDMA(Remote Direct Memory Access)를 Storm에 적용하는 설계안을 제시함으로써 CPU 과부하 문제를 해결한다.

• 한국시뮬레이션학회논문지
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• 제9권4호
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• ETRI Journal
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• 제19권3호
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• pp.186-201
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• 1997

In this paper, a home location register (HLR) for CDMA mobile communication system (CMS) is introduced. It stores the mobile station (MS) subscribers locations and supplementary service information. Call processing procedures for HLR are developed to receive and store subscriber's location coming from mobile exchange (MX) during the location registration, and to transfer subscriber's location and supplementary service information to the MX during the mobile-terminated call setup. For fast call processing by increasing database access speed, a memory-resident database management system is devised. For Easy and secure HLR operation, administration and maintenance functions and overload control mechanisms are implemented. Designed HLR hardware platform is expandable and flexible enough to reallocated software blocks to any subsystems within the platform. It is configurable according to the size of subscribers. An authentication center (AC) is developed on the same platform. It screens the qualified MS from the unqualified. The calls to and from the unqualified MS are rejected in CMS. To authenticate the MS, the AC generates a new authentication parameter called "AUTHR" using shared secret data (SSD) and compared it with the other AUTHR received from the MS. The MC also generates and stores seed keys called "A-keys" which are used to generate SSDs. The HLR requirements, the AC requirements, software architecture, hardware platform, and test results are discussed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.31-36
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• 2002

PBGA에 비해 상대적으로 큰 칩을 실장하는 고속 SRAM용 153 FC-BGA을 대상으로 2차 솔더접합부의 신뢰성을 평가하였다. 실험은 열사이클 시험에서 발생하는 단면과 양면 실장, 패키지 구조, 언더 필 재료, 기판의 종류와 두께, 솔더 볼의 크기에 따른 영향을 분석하였다. BT기판의 두께가 0.95mm에서 1.20mm로 증가하고, 낮은 영률 의 언더 필 재료에서 솔더접합부의 피로 수명이 30% 향상됨을 확인하였다. 또한 솔더 볼의 크기가 0.76 mm에서 0.89mm로 증가하면, 솔더접합부에서 균열에 대한 저항성은 2배 정도 증가하였다.

• 한국인터넷방송통신학회논문지
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• 제15권6호
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• pp.129-134
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• 2015

본 논문에서는 스마트폰 앱의 파일 접근 중 상당 부분이 1회성 쓰기 참조라는 것을 분석하고 이러한 특성을 고려한 버퍼캐쉬 관리 기법을 제안한다. 버퍼캐쉬는 여러 번 참조되는 파일 데이터를 스토리지 접근 없이 메모리에서 처리하여 성능 개선을 도모하지만, 쓰기 참조가 발생한 경우에는 짧은 시간 내에 스토리지에 직접 반영하여 시스템 크래쉬에 대비한다. 제안하는 기법은 1회의 쓰기만 발생한 캐쉬 데이터의 경우 스토리지 반영 직후 버퍼캐쉬에서 쫓아내어 캐쉬의 공간 효율을 높인다. 다양한 스마트폰 앱에 적용한 시뮬레이션 실험 결과 제안하는 기법은 기존 버퍼캐쉬 관리 기법에 비해 캐쉬적중률을 5-33% 향상시키고, 전력소모를 27-92% 줄일 수 있음을 보인다.

• 한국전기전자재료학회논문지
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• 제27권2호
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• pp.81-84
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• 2014

The bipolar resistive switching characteristics of resistive random access memory (ReRAM) based on $HfO_2$ thin films have been demonstrated by using Ag/$HfO_2$/Pt structured ReRAM device. MIcrowave irradiation (MWI) treatment at low temperature was employed in device fabrication with $HfO_2$ thin films as a transition layer. Compared to the as-deposited Ag/$HfO_2$/Pt device, highly improved uniformity characteristics of resistance values and operating voltages were obtained from the MWI treatment Ag/$HfO_2$/Pt ReRAM device. In addition, a stable DC endurance (> 100 cycles) and a high data retention (> $10^4$ sec) were achieved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.191-192
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• 2008

For phase transition method, good record sensitivity, low heat radiation, fast crystallization and hi-resolution are essential. Also, a retention time is very important part for phase-transition. In our past papers, we chose composition of $Ge_1Se_1Te_2$ material to use a Se factor which has good optical sensitivity than conventional Sb. Ge-Se-Te and Ag/$Ge_1Se_1Te_2$ samples are fabricated and irradiated with He-Ne laser and DPSS laser to investigate a reversible phase change by light. Because of Ag ions, the Ag layer inserted sample showed better performance than conventional one. We should note that this novel one showed another possibility for phase-change random access memory.

• 한국컴퓨터정보학회논문지
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• 제23권10호
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• pp.1-9
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• 2018

Modern graphics processing units (GPUs) have become one of the most attractive platforms in exploiting high thread level parallelism with the support of new programming tools such as CUDA and OpenCL. Recent GPUs has applied cache hierarchy to support irregular memory access patterns; however, L1 data cache (L1D) exhibits poor efficiency in the GPU. This paper shows that the L1D does not always positively affect the applications in terms of performance and energy efficiency for the GPU. The performance of the GPU is even harmed by using the L1D for lots of applications. Our proposed technique exploits the characteristics of the currently-executed applications to predict the performance impact of the L1D on the GPU and then decides whether to continuously use the cache for the application or not. Our experimental results show that the proposed technique improves the GPU performance by 9.4% and saves up to 52.1% of the power consumption in the L1D.