• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.694-698
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• 2004

In this paper, as one of these efforts for making the intelligent data mining system we propose the Associative frame of the memory according to the following three steps. First,the structured frame for performing the main brain function should be made. In this frame, the concepts of learning memory and episode memory are considered. Second,the learning mechanism for data acquisition and storing mechanism in the memory frame are provided. The obtained data are arranged and stored in the memory following the rules of the structured memory frame. Third, it is the last step of processing the inference and knowledge retrieval function using the stored knowledge in the associative memory frame. This system is applied to the area for estimating the purchasing degree from the type of customer's tastes, the pattern of commodities and the evaluation of a company.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• Journal of the Korea Society of Computer and Information
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• v.27 no.5
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• pp.11-19
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• 2022

In this paper, we propose a fault tolerant embedded system using memory redundancy on the full-virtualization based virtual machine monitor. The proposed virtual machine monitor first virtualizes main memory of embedded system utilizing efficient shadow page table scheme so that the embedded system runs as a virtual machine on the virtual machine monitor. The virtual machine monitor makes the backup of the embedded system run as another virtual machine by copying memory contents of the embedded system into memory space of backup system according to predefined schedules. When an error occurs in the target virtual machine, the corresponding standby virtual machine takes the role of target virtual machine and continues its operation. Performance evaluation studies show that such backups and switches of virtual machines are performed with minor performance degradation.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.

• Korean Journal of Cognitive Science
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• v.7 no.3
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• pp.7-36
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• 1996

Recebt neuropsychological studies on neurobiological bases of learning and memory in humans are reviewed. At present, cognitive psychologists belive that memory is not a unitary system. But copmosed of several independent subsystems. Adoption this perspective,this paper summarized findings regarding what kinds of memory discorders result from lesions of which brain areas and which brain areas are activated by what kind of learning/memory tasks. Short-term memory seems to involve widespread areas around the boundaries among the parietal,occipital,and temporal lobes,depending on the type of the type of the tasks and the way of presentation of the stimuli. Implicit memory,a subsystem of long-term memory,is not a unitary system itself. Thus,brain areas involved in implicit memory tasks used. It is well-known that medial temporal lobe is necessary for formation(i,e.,consolidation)of explicit memory,another subsystem of long-term memory. Storage and/or retrieval of episodic and semantic memory involve temporal neocortex. Perfromtal cortex seemas to be involved in several aspects of memory such as short term memory and retrieval of espisodic and semantic memory. Finally, a popular view on the locus of long-term memory storage is described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.11
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• pp.1041-1049
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• 2012

The transactional memory was proposed to solve the problems of the conventional lock-based synchronization methods in the shared memory multiprocessor system. Various implementation methods for putting the high performance transactional memory to practical use have been continuously studied. However, these studies focus only on the commercialization and performance enhancement of the transactional memory. Besides, there have been few studies to analyze the system overhead of the transactional memory according to the conflict management policy. Thus this paper classifies hardware transactional memory, which is one kind of transactional memories, into four types according to the conflict management policy, and then compares and analyzes their performance and system bus traffic through their modeling and simulation. In addition, the most effective conflict management policy for the hardware transactional memory is presented through these comparison and analysis.

• ETRI Journal
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• v.34 no.5
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• pp.787-790
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• 2012

The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.8 s.227
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• pp.1099-1108
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• 2004

In this paper, a study on the development of expert system for Al matrix composite with shape memory alloy fiber is performed to evaluate termomechanical behavior and mechanical properties. Expert system is very useful computer-based analysis system designed to make analysis technique and knowledge conveniently available to a lot of fabricable condition. In the developed system, it is possible to predict termomechanical behavior and mechanical properties for other composite with shape memory alloy fiber. The smartness of the shape memory alloy is given due to the shape memory effect of the TiNi fiber which generates compressive residual stress in the matrix material when heated after being prestrained. For finite element analysis, an analytical model is assumed two dimensional axisymmetric model compared of one fiber and the matrix. To evaluate the strength of composite using FEM, the concept of smart composite was simulated on computer Thus, in this paper, the FEA was carried out at two critical temperature conditions; room temperature and high temperature(363k). The finite element analysis result was compared with the test result for the analysis validity.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.6
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• pp.19-28
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• 2005

The multiprocessor architecture is a good method to improve the computer system performance. The CC-NUMA provides a single shared space with the physically distributed memories is used widely in the multiprocessor computer system. A CC-NUMA has the full-mapped directory for the shared memory md uses a remote cache memory for tile fast memory access. In this paper, we propose a processing node architecture for a CC-NUMA system and a cache coherency protocol on the physically distributed but logically shared system. We show an implementation result of the system which is adopted the cache coherency protocol.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.